Display device for sampling input image signals

ABSTRACT

A display device performs sampling of an input image signal for displaying by a dot matrix display element, and includes a selection unit for, in consonance with types of information to be displayed, selecting either to supply a predetermined pixel group with a signal that is obtained by sampling at a first timing, or to supply the predetermined pixel group with a signal that is obtained by sampling at a second, different timing. In addition, the display device, which performs sampling of input image signals and displays the resultant signal by using a dot matrix display element, includes a detection circuit for detecting character information that is included in the input image signal, and a unit for altering a method for processing the input image signal in consonance with an output of the detection circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device, such as a liquiddisplay device, a plasma display, an electrochromic device, a fieldemission display, or a digital micro mirror device, that has dot matrixelements in which display pixels are arranged during a predeterminedcycle.

2. Related Background Art

FIG. 29 is a diagram illustrating an example of an image device in whichdisplay pixels, for which luminance can be controlled by an inputcontrol signal, are arranged as multiple matrixes, and in which theluminance levels (display states) of display pixels correspond to inputimage signals. In FIG. 29, R1, G1 and B1 denote arbitrary portions ofdisplay pixels in a display device; and SR, SG and SB are image signalsthat are input to a liquid crystal display device and are supplied tored, green and blue display pixels. The red, green and blue pixels arehereinafter called dots. Although a set of three of the pixels maysometimes be called a pixel, in this case, an individual color pixel isregarded as one pixel.

Conventionally, when, by using an image signal, signal values r1, g1 andb1 are respectively acquired for display pixels R1, G1 and B1 bysampling during a cycle 3T, and a display is performed with theseobtained signal values, folded distortion of luminance signals isnoticeable on a display screen. In order to prevent the occurrence ofsuch folded distortion of luminance signals, a method is employed bywhich an image signal is used to perform sampling of the individualcolor pixels during a cycle T. By sampling during the cycle T, signalvalue r1 is acquired for display pixel R1 at time t1, signal value g2 isacquired for display pixel G1 at time t2, and signal value b3 isacquired for display pixel B1 at time t3. In other words, to performsampling this method matches the horizontal position of a display pixelwith the horizontal position of an image.

With this display method, the influence of the folded distortion of aluminance signal is reduced, but depending on the degree of change thatis carried by an input image signal, color moire appears on a displayscreen during a cycle that is shorter than the cycle T. To remove this,a method is employed by which low-pass filtering of an input imagesignal is performed.

However, according to the above described method, when an image signalis passed through a low-pass filter in order to remove color moire, asignal, which is in the vicinity of a sampling cycle and which isincluded in the original image signal, is also removed, so that theresolution of an image is reduced.

FIG. 30 is a block diagram illustrating a liquid crystal display device.In FIG. 30, reference number 401 denotes an input terminal of an imagesignal; 402, a signal processing circuit; 403, a synchronizingseparation circuit; 404, a controller; 405, an X-driver; 406, aY-driver; and 407, an XY matrix liquid crystal display (hereinafterreferred to as an LCD). The signal processing circuit 402 performs apredetermined process, such as γ compensation or inversion, on an imagesignal that is input at the input terminal 401 in order to display theimage signal. The processed signal is transmitted to the X-driver 405,and also to the synchronizing separation circuit 403, which separates asynchronization signal from the received signal. The separatedsynchronization signal is transmitted to the controller 404. In responseto the signal, the controller 404 supplies, to the X-driver 405 and theY-driver 406, a predetermined drive pulse, for driving the LCD 407, thatis synchronized with an image signal. The LCD 407 is driven by an imagesignal and a drive pulse that are supplied by the X-driver 405, and adrive pulse that is supplied by the Y-driver 406, and displays thereceived image signal.

FIG. 31 is a diagram illustrating the LCD 407 in FIG. 30. In FIG. 31,reference number 461 is used to denote individual switching devices,which are FETs; 462, individual liquid crystal cells; 463, individualsupport capacitors for supporting signal electrical charges; 464R, 464Gand 464B, individual input terminals for primary color signals (R, G andB) that are supplied by the X-driver 405; 465R, 465G and 465B,individual switching devices, which are FETs; 466, a common electrodefor the liquid crystal cells 462; 467R, 467G and 467B, individualterminals at which a drive pulse that is supplied by the X-driver 405 isinput; and 468, individual input terminals at which a drive pulse thatis supplied by the Y-driver 406 is input.

In the LCD shown in FIG. 31, the arrangement by color of the individualpixels corresponds to the R, G and B striped color filter arrangementthat is shown in FIG. 32.

FIG. 33A is a diagram illustrating the arrangement of the X-driver 405in FIG. 30, and FIG. 33B is a diagram illustrating the arrangement ofthe Y-driver 406. As is shown in FIGS. 33A and 33B, the X-driver 405 andthe Y-driver 406 are shift registers. In FIGS. 33A and 33B, referencenumber 421 denotes a terminal at which a start pulse for the shiftregister is input; 422, a terminal at which a drive pulse for the shiftregister is input; 423, D flip-flops; 424, terminals from which LCDdrive pulses that are transmitted by the X-driver 405 are output; 431, aterminal at which a drive pulse for the shift register is input; 433, Dflip-flops; and 434, terminals from which LCD drive pulses that aretransmitted by the Y-driver 406 are output.

The operation of a conventional LCD will now be described whilereferring to FIGS. 31, 33A and 33B. When a start pulse is received atthe input terminal 421 at the beginning of a horizontal scan period, andwhen a clock of m/3 times (m is the number of pixels in the horizontaldirection for a liquid crystal display device) a horizontal frequency isreceived at the input terminal 422, the shift register for m/3 stages inFIG. 33A is driven by the input driven pulse, and the output pulse ofthe shift register is transmitted to the output terminals 424. At thistime, one of the output terminals 424 is commonly connected to threeinput terminals 467R, 467G and 467B. When the same drive pulse that isoutput by the X-driver 405 is simultaneously supplied to the gates ofthe three switching devices, 465R, 465G and 465B, and all the switchesare thus turned on at the same time, sampling is performed for imagesignals that are simultaneously input at the input terminals 464R, 464Gand 464B, and the resultant signals are supplied to vertical signallines. One end of each of the switching devices 461 is connected to eachof the vertical lines, and the other end is connected to the liquidcrystal cell 462 and the capacitor 463. Therefore, signal writing issimultaneously performed for each three vertical scan lines, and as adrive pulse is sequentially output from the shift register of theX-driver 405, horizonal scanning is also performed. Furthermore, when astart pulse is input at the input terminal 431 at the beginning of avertical scan period, and a horizonal frequency clock is input at theinput terminal 432, the shift register having n stages (n is the numberof pixels in the vertical direction of a liquid crystal display device)in FIG. 33B is driven by the drive pulse, and the output pulse of theshift register is output to the output terminals 434. Each of the outputterminals 434 is connected to the input terminal 468. When a drive pulsethat is output by the Y-driver 406 is supplied to the gate of theswitching device 461 across a predetermined horizontal gate line, andeach switch is turned on, the liquid crystal cell 462 and the capacitor463 hold electric charges that correspond to potential differencesbetween signals that are supplied to the input terminals 464R, 464G and464B, and a voltage that is applied to the common electrode 466. At thistime, a predetermined voltage is provided for the common electrode 466.The above process is repeated and an image for one screen can bedisplayed on the LCD shown in FIG. 31.

So long as the number of pixels on the LCD is sufficient, a satisfactoryresolution can be acquired with the above described conventionalarrangement; however, if the number of pixels is increased for a smallLCD having a diagonal measurement of 10 cm or less, the dimension perpixel is reduced more than it is for a large LCD having a diagonalmeasurement of 20 cm or more, the rate of opening is reduced, and asatisfactory brightness can not be obtained. For this reason, the numberof pixels for an LCD can not be too greatly increased. Therefore, inorder to acquire a resolution having a satisfactory appearance whileusing an LCD that has a small number of pixels, an X-driver shown inFIG. 34 is used instead of the X-driver 405 in FIG. 33A. In FIG. 34, thesame reference numbers as are used in FIGS. 33A and 33B are used todenote corresponding or identical components. The X-driver in FIG. 34 isa stage shift register. When a start pulse is input at an input terminal421 at the beginning of the horizonal scan period, and a clock of mtimes a horizontal frequency is input at an input terminal 422, them-stage shift register in FIG. 33A is driven by the drive pulse, and anoutput pulse from the shift register is output to output terminals 424.One of the output terminals 424 is connected to three input terminals,467R, 467G and 467B. The drive pulse output by the X-driver issequentially supplied to the gates of switching devices 465R, 465G and465B, and switches are turned on in order. Then, at different timings,sampling of image signals that are input at input terminals 464R, 464Gand 464B is performed, and following the sampling, the signals aresupplied to vertical signal lines. The vertical scanning operation isperformed in the same manner as is described in the previousconventional example, and an image for one screen is displayed on theLCD in FIG. 31. By increasing the sampling frequency for horizontalimage signals, resolution is enhanced for an LCD having a small numberof pixels.

However, in the prior art in FIGS. 33A and 33B, since sampling isperformed at the three pixels R, G and B by using the same phase, asatisfactory resolution can not be obtained if an LCD has aninsufficient number of pixels. In addition, if sampling to remove theabove shortcoming is performed at the three pixels R, G and B atdifferent phases, as is described in FIG. 34, folded distortion (colormoire) that is caused by sampling is noticeable when fine images,especially characters, are displayed.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide a display devicethat can perform the high quality display of character information andnon-character information even though an inexpensive display elementthat has a comparatively small number of pixels is employed.

It is another object of the present invention to provide a displaydevice, which performs sampling of input image signals for displaying bya dot matrix display element, that comprises selection means for, inconsonance with types of information to be displayed, selecting eitherto supply a predetermined pixel group a signal that is obtained bysampling at a first timing, or to supply the predetermined pixel group asignal that is obtained by sampling at a second, different timing.

It is an additional object of the present invention to provide a displaydevice, which performs sampling of input image signals for displaying bya dot matrix display element, that comprises: a detection circuit fordetecting character information that is included in the input imagesignal; and means for altering a method for processing the input imagesignal in consonance with an output of the detection circuit.

To achieve the above objects according to the present invention, adisplay device, which performs sampling of an input image signal duringa predetermined cycle and acquires signal values for color signals, andwhich, based on these values, displays pixels for three colors, red,green and blue, that are arranged in a matrix form, comprises:comparison means, for comparing a difference between two signal values,which are selected from among the signal values obtained by sampling,with a predetermined threshold value; and means for, in consonance withan output of the comparison means, selectively switching a signal valuethat is to be provided for a display pixel.

The input image signal is either one or both of a pair of signals forcontrolling display pixels for red, green and blue, and a luminancesignal.

When sequential sampling of a luminance signal is performed at times t1,t2 and t3 (t1<t2<t3) and three signal values yn1, yn2 and yn3 areacquired, and when the three signal values correspond respectively toluminances for red, green and blue pixels that are sequentiallyarranged, the comparison means compares a difference between yn1 and yn2with a predetermined threshold value, and compares a difference betweenyn2 and yn3 with the predetermined value.

When sequential sampling of a luminance signal for a green pixel isperformed at times t1, t2 and t3 (t1<t2<t3) and three signal values gn1,gn2 and gn3 are acquired, and when, from among the three signal values,gn2 corresponds to a signal value that is provided for a green pixelfrom among red, green and blue pixels that are sequentially arranged,the comparison means compares a difference between gn1 and gn2 with apredetermined threshold value, and compares a difference between gn2 andgn3 with the predetermined value.

As means for selecting signal values from among signal values rn1, rn2and rn3, signal values gn1, gn2 and gn3, and signal values bn1, bn2 andbn3, which are acquired by sequentially sampling luminance signals forred, green and blue pixels, respectively, at times t1, t2 and t3(t1<t2<t3), and for providing a continuous red, green and blue pixelarrangement, the comparison means includes means for selecting eitherrn1 or gn2 and for providing the selected signal value for a red pixel;means for providing signal value gn for a green pixel; and means forselecting either bn3 or gn2 and providing the selected signal value fora blue pixel.

A display device, such as a liquid crystal display device, in whichdisplay pixels for red, green and blue (hereinafter referred to as R, Gand B) are arranged in a matrix form, can prevent color moire when animage is to be displayed as an image signal is input, and can alsoeffectively utilize for a display information concerning the input imagesignal.

Further, to achieve the above objects, according to the presentinvention, a display device, which performs sampling of an input imagesignal during a predetermined cycle and employs the sampled signals todisplay pixels for three colors, red, green and blue that are arrangedin a matrix form, comprises: sampling means for sequentially performingsampling, at times t1, t2 and t3 (t1<t2<t3), of signals for controllingred, green and blue display pixels in an input image signal, and forrespectively acquiring signal values rn1, rn2 and rn3, and gn1, gn2 andgn3, and bn1, bn2 and bn3; selection means for selecting three signalvalues from among the thus acquired signal values and for comparing adifference between two signal values, which are selected from among thesignal values obtained by sampling, with a predetermined value, andselecting and outputting three signal values in consonance with a resultof the comparison; and means for displaying corresponding red, green andblue pixels in consonance with the signal values that are selected.

Further, when the selection means compares a difference |rn1-rn2|between the signal values rn1 and rn2 with threshold value Th, and as aresult |rn1-rn2|>Th is established, or when the selection means comparesa difference |rn2-rn3| between the signal values rn2 and rn3 with thethreshold value Th, and as a result |rn2-rn3|>Th is established, theselection means selectively switches a signal value.

In addition, when the selection means compares a difference |gn1-gn2|between the signal values gn1 and gn2 with the threshold value Th, andas a result |gn1-gn2|>Th is established, or when the selection meanscompares a difference |gn2-gn3| between the signal values gn2 and gn3with the threshold value Th, and as a result |gn2-gn3|>Th isestablished, the selection means selectively switches a signal value.

Furthermore, when the selection means compares a difference |bn1-bn2|between the signal values bn1 and bn2 with the threshold value Th, andas a result |bn1-bn2|>Th is established, or when the selection meanscompares a difference |bn2-bn3| between the signal values bn2 and bn3with the threshold value Th, and as a result |bn2-bn3|>Th isestablished, the selection means selectively switches a signal value.

When the selection means compares a difference |rn1-gn2| between thesignal values rn1 and gn2 with the threshold value Th, and as a result|rn1-gn2|>Th is established, or when the selection means compares adifference |gn2-bn3| between the signal values gn2 and bn3 with thethreshold value Th, and as a result |gn2-bn3|>Th is established, theselection means selectively switches a signal value.

In consonance with the result of a comparison, the selection meanschanges the signal rn1, which is to be provided for the red pixel, andthe signal value bn3, which is to be provided for the blue pixel, to thesignal value gn1, gn2 or gn3.

The sampling means performs sampling for red, green and blue controlsignals at the times t1, t2 and t3 in order for the individual colors,and as a result, acquires further signal values Frn1, Frn2 and Frn3Fgn1, Fgn2 and Fgn3, and Fbn1, Fbn2 and Fbn3. In consonance with theresult of comparison, the selection means selects Frn1, Fgn2 and Fbn3from among the signal values.

In addition, to achieve the above objects, according to the presentinvention, a display device, which displays red, green and blue pixelsin consonance with corresponding red, green and blue signal values thatare acquired by sampling red, green and blue signals that are includedin an input image signal during a predetermined cycle, comprises:detection means for detecting a change value |A-B| between continuoussignal values A and B that are acquired by sampling; first comparisonmeans for comparing the signal value A with predetermined value L0;second comparison means for comparing the change value |A-B| withpredetermined value D0; and replacement means for, in consonance withresults of comparisons by the first and second comparison means,replacing a signal value, which is to be provided for a pixel for aspecific color, with a signal value for another color.

When a result of a comparison by the first comparison means is A<L0, anda result of a comparison by the second comparison means is |A-B|>D0, thereplacement means performs replacement of a signal value.

A display device, which displays red, green and blue pixels inconsonance with corresponding red, green and blue signal values that areacquired by sampling red, green and blue signals that are included in aninput image signal during a predetermined cycle, comprises: detectionmeans for detecting a change value |A-B| between continuous signalvalues A and B that are acquired by sampling; means for outputting apredetermined comparison value in consonance with the signal value A;means for comparing the change value |A-B| with the comparison value;and means for, in consonance with results of comparisons by the firstand the second comparison means, replacing a signal value, which is tobe provided for a pixel for a specific color, with a signal value foranother color.

A display device, which acquires red, green and blue signal values bysampling, during a predetermined cycle, for red, green and blue signalsthat are included in an input image signal, and which sequentiallyallocates the signal values for pixels of corresponding colors at eachtiming that is consonant with the cycle so as to display the pixels forindividual colors that are arranged in a matrix form, comprises:

detection means for, in consonance with sequential signal values and achange value for at least one color that are acquired by sampling,determining that color moire is noticeable; and

means, when it is determined that the color moire is noticeable, forallocating a signal value for a specific color to a pixel for adifferent color, instead of a signal value for the pixel for thedifferent color.

With this arrangement, when the result of the comparison by the firstcomparison means is A<L0, and the result of the comparison by the secondcomparison means is |A-B|>D0, the luminance is low in a pixel area thatcorresponds to the signal value and there is a change in the luminance,and as a result color moire tends to occur. In such a case, if a signalvalue for which there is a greater change in the luminance is employedto replace a signal value for another color, the appearance of colormoire in the above pixel area is prevented. On the other hand, when theluminance is high (A>L0), the replacement of a signal value is notperformed, the deterioration of a resolution is prevented, andinformation carried by an input image signal is displayed moreeffectively. In a case where the change value |A-B| is compared with apredetermined comparison value that is consonant with signal value A todetermine whether color moire will tend to appear, a value that isproportional to the signal value A can be employed as the predeterminedcomparison value, and thus the determination can be made moreaccurately.

Further, while color moire that occurs due to folded distortion throughsampling is reduced, information carried by an input image signal iseffectively displayed.

Since means for detecting a change pattern in the amplitude of an inputimage signal determines in which area color moire in which particularlytends to appear, and selectively switches a signal value that is to beprovided for a display pixel, information carried by an input imagesignal can be displayed more effectively.

In addition, to achieve the above objects, according to the presentinvention, provided is a liquid crystal display device, which comprises:

an XY matrix liquid crystal display,

sampling means for sampling an input image signal at a predeterminedtiming and supplying the resultant signal to the liquid crystal display,and

synthesizing means for adding character information to the input imagesignal, or character region discrimination means for identifying, fromthe input image signal, a region in which the character information isincluded; and

wherein, for a region in which character information is not displayed,the sampling means supplies image signals with different phases thatspatially match in a phase display positions of all pixels on the liquidcrystal display, and wherein, for a region of the liquid crystal displayin which character information is displayed, the sampling means suppliesan image signal of the same phase, which spatially matches a displayposition of a specified pixel in a pair of given pixels that areadjacent and that each consist of one dot of the liquid crystal display,to each pair of the given pixels.

For a region in which character information is not displayed, thesampling means performs sampling at different timings at which phasesspatially match display positions of the pixels on the liquid crystaldisplay, and acquires image signals that are to be supplied to thepixels. For a region of the liquid crystal display in which characterinformation is displayed, the sampling means performs sampling at thesame timing at which a phase spatially matches a display position of thespecified pixel of the given pixels on the liquid crystal display, andacquires an image signal that is to be supplied to the given pixels.

Further provided is delay means for delaying the image signal apredetermined time. The sampling means performs sampling at differenttimings, at which phases spatially match the display positions of thepixels on the liquid crystal display, to acquire signals that are to besupplied to the pixels. For a region in which character information isdisplayed, the delay means supplies the image signal to the samplingmeans after a delay so that the sampling means performs sampling of asignal, which is to be supplied to the given pixels, at the same timingat which a phase spatially matches the display position of the specifiedpixel of the given pixels. For a region in which character informationis not displayed, the delay means supplies the image signal to thesampling without any delay.

Provided in addition is delay means for delaying the image signal apredetermined time. The sampling means performs sampling at the sametiming at which a phase spatially matches the display position of thespecified pixel of the given pixels, to acquire signals that are to besupplied to the given pixels. For a region in which characterinformation is not displayed, the delay means supplies the image signalafter a delay to the sampling means so that the sampling means performssampling of a signal, which is to be supplied to the given pixels, atdifferent timings at which phases spatially match the display positionsof the given adjacent pixels. For a region in which characterinformation is displayed, the delay means supplies the image signal tothe sampling means without any delay.

According to the present invention, for a region in which characterinformation is not displayed, image signals at different phases thatspatially match the display positions of the pixels in a liquid crystaldisplay are supplied to the individual pixels. For a region in whichcharacter information is displayed, an image signal of the same phase,which spatially matches the display position of a specified pixel of aplurality of pixels that form one dot of a liquid crystal display, issupplied to each of those pixels. Therefore, folded distortion can beprevented from occurring when character information is to be displayed.

When the delay means is provided, a conventional X-driver is applied toprovide a liquid crystal display device that performs the same functionsas are described above.

According to the present invention, provided is a display device, whichcomprises:

a display of dot matrix type,

sampling means for performing sampling of an input signal at apredetermined timing and for supplying a resultant signal to thedisplay,

signal production means for producing a luminance signal and a colorsignal from an input image signal,

signal level detection means for detecting signal levels of theluminance signal and the color signal, and

character region discrimination means for employing a result of adetection by the signal level detection means to identify a region in aninput image where character information is included, so that the inputimage that includes the character information is displayed on thedisplay,

wherein the character region discrimination means determines that adisplay image is the region in which character information is includedwhen the signal level of the luminance signal that is detected by thesignal level detection means is higher than a predetermined value; andthe signal level of the color signal is lower than a predeterminedvalue, and wherein, for a region in which character information is notdisplayed, the sampling means performs sampling at different timings, atwhich phases spatially match display positions of the pixels on thedisplay, and acquires image signals that are to be supplied to thepixels, and, for a region in which character information is displayed,the sampling means performs sampling, at the same timing at which aphase spatially matches a display position of a specified pixel of threespecific pixels on the display, and acquires an image signal that is tobe supplied to the three specific pixels, so that folded distortion isprevented when character information is added to an input image and isdisplayed on the display.

According to the present invention, provided is a display device, whichcomprises:

a display of dot matrix type,

sampling means for performing sampling of an input signal at apredetermined timing and for supplying a resultant signal to thedisplay,

signal production means for producing a luminance signal and a colorsignal from an input image signal,

signal level change detection means for detecting a degree of change insignal levels of the luminance signal and the color signal, and

character region discrimination means for employing a result of adetection by the signal level detection means to identify a region in aninput image where character information is included, so that the inputimage that includes the character information is displayed on thedisplay,

wherein the character region discrimination means determines that adisplay image is the region in which character information is includedwhen a degree of change in the signal level of the luminance signal,which is detected by the signal level detection means, is higher than apredetermined value and a degree of change in the signal level of thecolor signal is lower than a predetermined value; and wherein, for aregion of the display in which character information is not displayed,the sampling means performs sampling at different timings at whichphases spatially match display positions of pixels on the display andacquires image signals that are to be supplied to the pixels, and, for aregion in which character information is displayed, the sampling meansperforms sampling at the same timing at which a phase spatially matchesa display position of a specified pixel of three specified pixels on thedisplay and acquires an image signal that is to be supplied to the threespecified pixels, so that folded distortion is prevented when characterinformation is added to an input image and is displayed on the display.

According to the present invention, provided is a display device, whichcomprises:

a display of dot matrix type,

sampling means for performing sampling of an input signal at apredetermined timing and for supplying a resultant signal to thedisplay,

delay means for delaying an image signal a predetermined time;

signal production means for producing a luminance signal and a colorsignal from an input image signal,

signal level detection means for detecting signal levels of theluminance signal and the color signal, and

character region discrimination means for employing a result of adetection by the signal level detection means to identify a region in aninput image where character information is included, so that the inputimage that includes the character information is displayed on thedisplay,

wherein the character region discrimination means determines that adisplay image is the region in which character information is includedwhen the signal level of the luminance signal that is detected by thesignal level detection means is higher than a predetermined value andthe signal level of the color signal is lower than a predeterminedvalue; and wherein, for a region in which character information is notdisplayed, a signal that is delayed by the delay means for thepredetermined time is supplied to the sampling means and the samplingmeans performs sampling of the signal at the same timing at which aphase spatially matches a display position of a specified pixel of threepixels, and, for a region in which character information is displayed, asignal is supplied to the sampling means without any delay by the delaymeans, and the sampling means performs sampling at the same timing atwhich a phase spatially matches the display position of the specifiedpixel of the three specific pixels, so that a conventional X-driver isapplied to prevent folded distortion when character information is addedto an input image and is displayed on the display.

According to the present invention, provided is a display device, whichcomprises:

a display of dot matrix type,

sampling means for performing sampling of an input signal at apredetermined timing and for supplying a resultant signal to thedisplay,

delay means for delaying an image signal a predetermined time;

signal production means for producing a luminance signal and a colorsignal from an input image signal,

signal level detection means for detecting signal levels of theluminance signal and the color signal, and

character region discrimination means for employing a result of adetection by the signal level detection means to identify a region in aninput image where character information is included, so that the inputimage that includes the character information is displayed on thedisplay,

wherein the character region discrimination means determines that adisplay image is the region in which character information is includedwhen the signal level of the luminance signal, which is detected by thesignal level detection means, is higher than a predetermined value andthe signal level of the color signal is lower than a predeterminedvalue; and wherein, for a region in which character information is notdisplayed, a signal is supplied to the sampling means without any delayby the delay means and the sampling means performs sampling at differenttimings at which phases spatially match display positions of individualpixels, and, for a region in which character information is displayed, asignal that is delayed by the delay means for the predetermined time issupplied to the sampling means and the sampling means performs samplingof the signal at different timings at which phases spatially matchdisplay positions of the individual pixels, so that a conventionalX-driver is applied to prevent folded distortion when characterinformation is added to an input image and is displayed on the display.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a display device according to afirst embodiment of the present invention;

FIG. 2 is a timing chart for controlling the display device of thepresent invention;

FIG. 3 is a diagram showing an output of a D/A converter;

FIG. 4 is a diagram for explaining signal processing performed by thedisplay device of the present invention;

FIG. 5 is a block diagram illustrating a control system for a displaydevice according to a second embodiment of the present invention;

FIG. 6 is a block diagram illustrating a control system for a displaydevice according to a third embodiment of the present invention;

FIG. 7 is a diagram showing an output of a timing generator;

FIG. 8 is a block diagram illustrating a control system for a displaydevice according to a fourth embodiment of the present invention;

FIG. 9 is a block diagram illustrating a control system for a displaydevice according to a fifth embodiment of the present invention;

FIG. 10 is a block diagram illustrating the arrangement of a displayelement according to the present invention;

FIG. 11 is a diagram showing an output of a timing generator;

FIG. 12 is a block diagram illustrating a control system for a displaydevice according to a sixth embodiment of the present invention;

FIG. 13 is a diagram showing an input-output characteristic of a signalprocessing circuit;

FIG. 14 is a block diagram illustrating a control system for a displaydevice according to a seventh embodiment of the present invention;

FIG. 15 is a circuit diagram illustrating a driver for the displayelement that is employed in this invention;

FIG. 16 is a block diagram illustrating a control system for a displaydevice according to an eighth embodiment of the present invention;

FIG. 17 is a diagram illustrating one arrangement of a delay circuitthat is used for the present invention;

FIG. 18 is a diagram illustrating another arrangement for the delaycircuit that is used for the present invention;

FIGS. 19A and 19B are diagrams showing a sample hold pulse for the delaycircuit shown in FIG. 18;

FIG. 20 is a diagram illustrating the arrangement of a delay circuitthat is used for a ninth embodiment of the present invention;

FIG. 21 is a diagram illustrating an additional arrangement for thedelay circuit that is used for the present invention;

FIGS. 22A and 22B are diagrams showing a sample hold pulse for the delaycircuit shown in FIG. 21;

FIG. 23 is a block diagram illustrating a control system for a displaydevice according to a tenth embodiment of the present invention;

FIG. 24 is a block diagram illustrating a control system for a displaydevice according to an eleventh embodiment of the present invention;

FIG. 25 is a diagram illustrating the arrangement of a character regiondiscrimination circuit that is employed for the display device of thepresent invention;

FIG. 26 is a diagram illustrating the arrangement of a character regiondiscrimination circuit that is employed for a display device accordingto a fourteenth embodiment of the present invention;

FIG. 27 is a circuit diagram illustrating a color signal level changedetection circuit that is employed for the present invention;

FIG. 28 is a circuit diagram illustrating a frequency detection circuitthat is employed for the present invention;

FIG. 29 is a specific diagram for explaining the relationship between asampling timing for input image signals and for display pixels;

FIG. 30 is a block diagram illustrating a conventional display device;

FIG. 31 is a circuit diagram illustrating a liquid crystal element;

FIG. 32 is a plan view of the arrangement of color pixels that is usedfor a display element;

FIGS. 33A and 33B are circuit diagrams illustrating one example of adriver for a display element;

FIG. 34 is a circuit diagram illustrating another example of a driverfor a display element;

FIG. 35 is a specific timing chart for explaining the relationshipbetween a sampling timing for input image signals and for display pixelsfor the display device of the present invention; and

FIG. 36 is a block diagram illustrating a control system for the displaydevice of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will now bedescribed. The basic structure will be described before specificarrangements are explained in detail while referring FIGS. 1 through 28.

FIG. 35 is a timing chart for sampling that is performed by a displaydevice for the present invention.

According to the present invention, in a mode in which is displayedcharacter information, such as alphabets, Greek letters, Roman numerals,Arabic numerals, the Japanese syllabary, or Chinese characters, colorsignal r1 at phase t1 is supplied to red pixel R1, color signal g1 issupplied to green pixel G1, and color signal b1 is supplied to pixel B1.Similarly, color signals r4, g4 and b4 at phase t4 are respectivelysupplied to color pixels R2, G2 and B2.

In another mode for displaying non-character information, such as forlandscape scenes and portraits that are recorded by a video camera,signal r1 at phase t1 is supplied to pixel R1, signal g2 at phase t2 issupplied to pixel G1, and signal b3 at phase t3 is supplied to pixel B1.

Similarly, at phases t4, t5 and t6, signals r4, g5 and b6 arerespectively supplied to pixels R2, G2 and B2.

Color signals may be supplied to corresponding pixels without anychange, or may be amplified and modified into a signal having adifferent waveform and be supplied to pixels. This is determined asneeded by the characteristic of a display element and the structure ofan XY driver.

FIG. 36 is a block diagram illustrating the structure in the displaydevice of the present invention for detecting character information andswitching the two above described modes in consonance with the result ofa detection.

A detection circuit determines whether or not character information ispresent, and in consonance with the result of a determination, a methodis decided on for distributing color signals that are obtained bysampling to pixels.

The time at which a mode is switched may be after one frame has beencompleted, but preferably is after one horizontal scan period has beencompleted.

In this manner, information for an image wherein characters are writtento a landscape image can be appropriately displayed, and such a displaydevice can serve as a multi-media device.

First Embodiment!

FIG. 1 is a block diagram illustrating a TFT liquid crystal paneldisplay device according to a first embodiment of the present invention.In FIG. 1, reference number 1 denotes input terminals for image signalsSY, SR, SG and SB. A/D converters 2 each sample a received image signaland hold the resultant signal, and convert it into a digital signalvalue. The signal values are held until the following signals areoutput.

A signal switching device 3 selects one of three signal values, and asignal switching device 10 selects one of two input signal values. Anoutput signal is held until the following signal is output. A timing forselection is supplied by an external timing generator 4, which will bedescribed in detail later. Timing generators 4 and 14 generate differenttiming signals from respective cycle signals that they receive. Memories5 and 6 are employed to store one signal value that is input. When thefollowing signal value is input, the previously stored signal value iserased. An arithmetic operation unit 7 calculates an absolute value fora difference between two received signal values. A memory 8 is used tostore a threshold value that is set in advance. A comparator 9 comparesa signal value output by the arithmetic operation unit 7 with thethreshold value that is stored in the memory 8. A timing for performingthe comparison is supplied by the timing generator 4. Reference number11 denotes an output terminal of the switching device 10. A clockgenerator 12 supplies a cycle signal for the entire display device.Reference number 13 denotes an output signal terminal for the clockgenerator 12. A D/A converter 15 has an input buffer in which threesignal values are stored, and converts each signal value in the bufferinto an analog signal at a timing that is supplied by the timinggenerator 14. The analog signals that are output are held until thefollowing signals are output. Reference number 18 denotes a liquidcrystal panel; 16, a row electrode driving circuit of the liquid crystalpanel; a column electrode driving circuit 17 of the liquid crystalpanel; and 19, the block diagram of a section enclosed by the brokenline.

FIG. 2 is a timing chart for the operations of the individual sections.A waveform shown in FIG. 2 is to be output by the timing generator 4 tothe individual sections. In synchronization with this waveform, theindividual sections of the display device perform signal processing.Ck1, 2, 3, . . . indicate timing counts whose numbers correspond withthe numbers of the clock pulse counts. The processing will now bedescribed while referring to FIGS. 1 and 2.

At clock (Ck) 1, sampling is performed of signals that are input at theimage input terminals 1, and the resultant signals are converted intodigital data by the A/D converter 15 to acquire signal values yn1, rn1,gn1 and bn1for respective signals. At Ck4, the switching device 3selects and outputs signal value rn1 of signal SR. At Ck5, signal valueyn1 for signal SY is stored in M5 and signal value rn1for signal SR isstored in M6. At Ck6, sampling of signals that are input at the imageinput terminals 1 is performed and the resultant signals are convertedinto digital data to acquire signal values yn2, rn2, gn2 and bn2 forrespective signals. At Ck7, the switching device 3 selects and outputssignal value gn2 of signal SG; and the arithmetic operation unit 7calculates as an absolute value a difference between signal values yn1and yn2 that are stored in M5. At Ck8, the comparator 9 compares theoutput of the arithmetic operation unit 7 with a threshold value th thatis written in advance in FR8. At Ck9, in consonance with the output ofthe comparator 9, the switching device 10 selects either rn1 or gn2 thatis stored in M6 and outputs the selected signal value to the signaloutput terminal 11. This signal value is held in the input buffer of theD/A converter 15. At Ck10, signal value yn2 for signal SY is stored inM5, and signal value gn2 for signal SG is stored in M6. At Ck11,sampling of signals that are input at the image input terminals 1 isperformed and the resultant signals are converted into digital data toacquire signal values yn3, rn3, gn3 and bn3 for respective signals; andthe switching device 10 outputs signal value gn2 for signal SG to thesignal output terminal 11. The output signal value is held in the inputbuffer of the D/A converter 15. At Ck12, the switching device 3 selectsand outputs signal value bn3 of signal SB; and the arithmetic operationunit 7 calculates as an absolute value a difference between signalvalues yn2 and yn3 that are stored in M5. At Ck13, the comparator 9compares the output of the arithmetic operation unit 7 with thethreshold value th that is written in advance in FR8. At Ck14, inconsonance with the output of the comparator 9, the switching device 10selects either gn2 or bn3 that is stored in M6 and outputs the selectedsignal value to the signal output terminal 11. The output signal valueis held in the input buffer of the D/A converter 15. The signal that isoutput at the signal output terminal 11 is processed by the D/Aconverter 15.

In FIG. 3 is shown an output signal of the D/A converter 15. The outputsignal from the switching device 10 is stored in the input buffer of theD/A converter 15 at Ck 9, Ck11 and Ck14, and is output from the D/Aconverter 15 during a period extending from Ck16 through Ck30, as isshown in FIG. 3. At this time, signal levels on1, on2 and on3 are valuesof analog signals into which the D/A converter 15 converts digitalsignals that are output by the switching device 10 at Ck 9, Ck11 andCk14. In response to the signal levels on1, on2, and on3 display pixelsR, G and B are turned on.

The process at Ck1 through Ck30 is hereinafter repeated.

FIG. 4 is a diagram showing specific signal process examples forcomparison and selection. The notation th denotes a threshold value.These process examples will now be explained while referring to FIG. 4.

In process 1, since |yn1-yn2|<th, signal value rn1is used for displayinga red display pixel. Further, since |yn2-yn3|>th, signal value gn2 isused instead of bn3 to display a blue display pixel.

In process 2, since |yn1-yn2|<th, signal value rn1is used for displayinga red display pixel. Further, since |yn2-yn3|>th, signal value gn2 isused instead of bn3 to display a blue display pixel.

In process 3, since |yn1-yn2|>th, signal value gn2 is used instead ofrn1to display a red display pixel. Further, since |yn2-yn3|<th, signalvalue gn3 is used to display a blue display pixel.

In process 4, since |yn1-yn2|>th, signal value gn2 is used instead ofrn1to display a red display pixel. Further, since |yn2-yn3|<th, signalvalue gn3 is used to display a blue display pixel.

Second Embodiment!

FIG. 5 is a diagram illustrating a block 22, which is equivalent to theblock 19 shown in FIG. 1, of the TFT liquid crystal panel display deviceaccording to a second embodiment of the present invention. Thearrangements for the other blocks are the same as those in FIG. 1. InFIG. 5, reference number 20 denotes input terminals for image signalsSR, SG and SB. Each of the A/D converters 21 samples a received imagesignal and holds the resultant signal, and converts it into a digitalsignal value. Although in the first embodiment signal SY is employed foran input to the comparison means, in this embodiment signal SG is usedinstead. Therefore, the structure for this embodiment can be simplerthan that for the first embodiment.

The operation of the display device will now be described.

A waveform that is output by a timing generator 4 in the secondembodiment is the same as that shown in FIG. 2. In synchronization withthis waveform, the individual sections of the display device performsignal processing.

At Ck1, sampling of signals that are input at the signal input terminals20 is performed and the resultant signals are converted into digitaldata to acquire signal values rn1, gn1 and bn1for respective signals. AtCk4, the switching device 3 selects and outputs signal value rn1forsignal SR. At Ck5, signal value gn1 for signal SG is stored in memory 5and signal value rn1for signal SR is stored in memory 6. At Ck6,sampling of signal that are input at the signal input terminals 20 isperformed and the resultant signals are converted into digital data toacquire signal values rn2, gn2 and bn2 for respective signals. At Ck7,the switching device 3 selects and outputs signal value gn2 for signalSG; and the arithmetic operation unit 7 calculates as an absolute valuea difference between signal values gn1 and gn2 that are stored in thememory 5. At Ck8, the comparator 9 compares the output of the arithmeticoperation unit 7 with a threshold value th that is written in advance inmemory 8. At Ck9, in consonance with the output of the comparator 9, theswitching device 10 selects either rn1or gn2 that is stored in thememory 6 and outputs the selected signal value to the signal outputterminal 11. This signal value is held in the input buffer of the D/Aconverter 15. At Ck10, signal value gn2 for signal SG is stored in thememories 5 and 6 at the same time. At Ck11, sampling of signals that areinput at the image input terminals 20 is performed and the resultantsignals are converted into digital data to acquire signal values rn3,gn3 and bn3 for respective signals; and the switching device 10 outputssignal value gn2 of signal SG to the signal output terminal 11. At Ck12,the switching device 3 selects and outputs signal value bn3 of signalSB; and the arithmetic operation unit 7 calculates as an absolute valuea difference between signal values gn2 and gn3 that are stored in thememory 5. The output signal value is held in the input buffer of the D/Aconverter 15. At Ck13, the comparator 9 compares the output of thearithmetic operation unit 7 with the threshold value th that is writtenin advance in the memory 8. At Ck14, in consonance with the output ofthe comparator 9, the switching device 10 selects either gn2 or bn3 thatis stored in the memory 6 and outputs the selected signal value to thesignal output terminal 11. The output signal value is held in the inputbuffer of the D/A converter 15. The signal that is output at the signaloutput terminal 11 is processed by the D/A converter 15.

In FIG. 3 is shown an output signal of the D/A converter 15. The outputsignal from the switching device 10 is stored in the input buffer of theD/A converter 15 at Ck9, Ck11 and Ck14, and is output from the D/Aconverter 15 during a period extending from Ck16 through Ck30, as isshown in FIG. 3. At this time, signal levels on1, on2 and on3 are valuesof analog signals into which the D/A converter 15 converts digitalsignals that are output by the switching device 10 at Ck9, Ck11 andCk14. In response to the signal levels on1, on2, and on3 display pixelsR, G and B are turned on.

The process at Ck1 through Ck30 is hereinafter repeated.

As is described above, according to the first and the second embodimentsof the present invention, a display device, comprising comparison meansfor comparing a difference between two signal values, which are selectedfrom among the signal values obtained by sampling, with a predeterminedthreshold value, and means for, in consonance with an output of thecomparison means, selectively switching a signal value that is to beprovided for a display pixel, can prevent color moire when an image isto be displayed as an input image signal is input, and can alsoeffectively utilize for a display information concerning the input imagesignal.

Third Embodiment!

FIG. 6 is a block diagram illustrating a TFT liquid crystal paneldisplay device according to a third embodiment of the present invention.Reference numbers 201R, 201G and 201B denote input terminals for imagesignals SR, SG and SB. A clock generator 202 supplies a signal to atiming generator, which will be described later. A timing generator 203supplies an operating clock to each section. A/D converters 204R, 204Gand 204B holds signals obtained by sampling image signals SR, SG and SB,and converts these signals into digital signal values. These signalvalues are held until the following signal is output. The sampling isperformed synchronously with signal φ1, which is supplied from thetiming generator 203. Shift registers 205R, 205G and 205B store in orderthree signal values that are output at a predetermined time intervalfrom the A/D converters 204R, 204G and 204B, and output them at the sametime from three output terminals. The values for input signals on whichsampling is performed at different times can be obtained from the outputterminals. The shift operation is performed synchronously with signalφ2, which is supplied by the timing generator 203. Signal switchingdevices 206R, 206G and 206B each select and output two arbitrarysignals, each of which may correspond to one selected by anotherswitching device. Flip-flops 207A through 207F hold data for theselected signals in synchronization with the rise of signal φ3, which issupplied by the timing generator 203. From among the three signals thatare received from the flip-flops 207A, 207B and 207C, a signal switchingdevice 208 selects and outputs two signals in synchronization withsignals φ4 and φ5 that are received from the timing generator 203. Asubtracter 209 that calculates as an absolute value a difference betweenthe two input signals. A ROM 210 is provided in which is stored athreshold value that is set in advance. A comparator 211 compares asignal from the subtracter 209 with a signal from the ROM 210 andoutputs the result of the comparison. A timing generator 212 suppliessignals to a signal switching device 213 and an FIFO memory 214, whichwill be described later. The signal switching device 213 has threesignal switching element pairs, a, b and c, each of which selects andoutputs one signal of the two that are input. The signal switchingdevice 213 has an internal counter, and switches the input signals inthe order represented by the letters of the signal switching elements a,b and c. The signal switching in the signal switching device 213 iscontrolled by using an output signal of the comparator 211, and isperformed in synchronization with signal φ6, which is supplied by thetiming generator 212. The internal counter is reset by using signal φ9,which is supplied by the timing generator 212. The FIFO memory 214stores a signal in synchronization with signal φ7, which is supplied bythe timing generator 212, and outputs the stored signal insynchronization with signal φ8, which is supplied by the timinggenerator 212. Reference number 215 denotes a signal terminal. A timinggenerator 216 supplies a synchronization signal to a column electrodedriving circuit and a row electrode driving circuit that, together withthe timing generator 216, are provided in a liquid crystal panel 217,which is a block enclosed by broken lines.

FIG. 7 is a timing chart for signals φ1 through φ9 that are output bythe timing generators 203 and 212. The individual sections of thedisplay device perform signal processing synchronously with thesewaveforms.

First, at time ta, upon receipt of signal φ1 from the timing generator203, the A/D converters 204R, 204G and 204B each sample signals that areinput at the respective terminals 201R, 201G and 201B, and hold theresultant signals. These signals that are obtained by samplingcorrespond to signal values r1, g1 and b1.

At time tb, upon receipt of signal φ2 from the timing generator 203, theshift registers 205R, 205G and 205B store and shift signals that areoutput from the A/D converters 204R, 204G and 204B, respectively.

During periods between times tc and td, and between te and tf, the A/Dconverters 204R, 204G and 204B, and the shift registers 205R, 205G and205B perform the above described operation. Through this process, theshift register 205R transmits signal value r1, r2 and r3 to the signalswitching device 206R; the shift register 205G transmits signal valuesg1, g2 and g3 to the signal switching device 206G; and the shiftregister 205B transmits signal values b1, b2 and b3 to the signalswitching device 206B. From among the three signal values that arereceived, each of the signal switching devices 206R, 206G and 206Bselects two predetermined signal values, each of which may correspond toa signal value selected by another switching device. In this embodiment,it is assumed that the signal switching device 206R is so set to outputsignal value r1, the signal switching device 206G is set to outputsignal value g2, and the signal switching device 206B is set to outputsignal value b3.

At time tg, in synchronization with signal φ3, which is supplied by thetiming generator 203, the flip-flops 207A through 207F hold and outputsignal values that are received from the signal switching devices 206R,206G and 206B. In this embodiment, according to the above assumption,the flip-flops 207A, 207B, 207C, 207D, 207E and 207F hold the respectivesignal values r1, g2, b3, r1, g2 and b3. The flip-flops 207A through207C output their signal values to the signal switching device 208.

At time th, in synchronization with signal φ4 from the timing generator203, the signal switching device 208 selects two given signals fromamong the signals that are received from the flip-flops 207A, 207B and207C. In this embodiment it is assumed that the signal switching device208 is set in advance to select signal value r1 from the flip-flop 207Aand signal value g2 from the flip-flop 207B in response to signal φ4.The subtracter 209 calculates as an absolute value a difference betweenthe two signal values r1 and g2, which are selected by the signalswitching device 208, and outputs the absolute value. The comparator 211compares the output of the subtracter 209 with the threshold value Th ofthe ROM 210, and outputs the result of the comparison. The comparator211 determines whether the output of the subtracter 209>Th isestablished, i.e., "true" or "false", and outputs the result as a binarysignal. When this condition is established, the comparator 211 outputs a"true" signal.

At time ti, if the signal received from the comparator 211 is "true",the signal switching device 213 selects the input terminal a2 of thesignal switching device 213. If the received signal is "false", theswitching device 213 selects the input terminal a2. The result of aselection is transmitted to the output terminal O. This selectionprocess is performed in synchronization with the receipt of signal φ6from the timing generator 212. When the output of the comparator 211 is"true", signal value r1 is input at the input terminal a1 of te signalswitching device 213, signal value g2 is input at the input terminal a2,and r1 is sent to the output terminal O. In this case, presume that r1is output from the output terminal O.

At time tj, in response to signal φ7 from the timing generator 212, theFIFO memory 214 stores signal value r1, which is output by the signalswitching device 213.

At time tk, the signal switching device 213 forwards the signal valuefrom the input terminal b2 to the output terminal O. At this time, theoutput of the comparator 211 is not employed. Signal value g2 isselected in this embodiment. At the same time, at time tk, the FIFOmemory 214 outputs signal value r1, which was stored at time tj, andholds the output signal value until time to. The signal that is outputby the FIFO memory 214 passes through the terminal 215 and is displayedon the liquid crystal panel 217.

At time t1, in synchronization with signal φ5 from the timing generator203, the signal switching device 208 selects and outputs two givensignals from among the signals that are received from the flip-flops207A, 207B and 207C. In this embodiment, it is assumed that the signalswitching device 208 is set in advance to select signal values that areoutput by the flip-flops 207B and 207C in response to signal φ5. Thus,the signal switching device 208 outputs signal values g2 and b3. At thesame time, at time t1, upon receipt of signal φ7 from the timinggenerator 212, the FIFO memory 214 stores signal value g2 that isselected by the signal switching device 213.

At time tm, in consonance with a "true" signal or a "false" signal thatis received from the comparator 211, the signal switching device 213selects a signal value input at either the input terminal c1 or c2 ofthe signal switching device 213, and outputs it to the output terminalO. This selection is performed in synchronization with signal φ6, whichis supplied by the timing generator 212. In this embodiment, it isassumed that signal value g2 is input at the input terminal c1 of thesignal switching device 213, signal b3 is input at the input terminalc2, and g2 is forwarded to the output terminal O.

At time tn, the FIFO memory 214 stores signal value g2 from the signalswitching device 213 (a signal value that was selected at time tm) inresponse to signal φ7, which is supplied by the timing generator 212.

At time to, the FIFO memory 214 outputs signal value g2 that was storedat time t1, and maintains the output signal value until time tp. Theoutput signal value is displayed on the liquid crystal panel 217.

At time tp, the FIFO memory 214 outputs signal value g2 that was storedat time tn. The output signal value is displayed on the liquid crystalpanel 217.

The above described process is repeated during cycle PT. Therelationship between times T and PT is PT=3T.

Fourth Embodiment!

FIG. 8 is a block diagram illustrating the arrangement of a displaydevice according to a fourth embodiment of the present invention. Thefourth embodiment will now be described while referring to FIGS. 7 and8. The same reference numbers as are used in FIG. 6 are also used inFIG. 8 to denote corresponding or identical components. In FIG. 8,signal filters 218R, 218G and 218B perform predetermined filtration ofsignals that are input at signal input terminals 201R, 201G and 201B,respectively. A/D converters 219R, 219G and 219B hold signal values thatare obtained by sampling signals that are output by the respectivesignal filters 218R, 218G and 218B, and convert the signals into digitalsignal values. The signal values are held until the following signalsare output. Sampling is performed in synchronization with signal φ1,which is supplied by a timing generator 203. Shift registers 220R, 220Gand 220B function the same as the shift registers 205R, 205G and 205B.Signal switching devices 221R, 221G and 221B each select, from amongthree received signal values, one signal value that is determined inadvance, and output the selected signal value. Flip-flops 222A, 222B and222C have two input terminals and two output terminals, and hold data insynchronization with the rise of signal φ3, which is supplied by thetiming generator 203. The flip-flops 222A, 222B and 222C hold theoutputs of signal switching devices 206R, 206G and 206B, and the outputsof the signal switching devices 221R, 221G and 221B, respectively.

The operation of the display device in the fourth embodiment will now bedescribed while referring to FIGS. 7 and 8.

First, at time ta, upon receipt of signal φ1 from the timing generator203, the A/D converters 204R, 204G and 204B each sample signals input atthe respective terminals 201R, 201G and 201B, and hold the resultantsignals. At the same time, the A/D converters 219R, 219G and 219B eachsample the respective output of the signal filters 218R, 218G and 218B,and hold the resultant signals.

At time tb, upon receipt of signal φ2 from the timing generator 203, theshift registers 205R, 205G and 205B store and shift signals that areoutput by the A/D converters 204R, 204G and 204B, respectively. At thesame time, the shift registers 220R, 220G and 220B store and shiftvalues of signals that are output by the A/D converters 219R, 219G and219B, respectively.

During periods between times tc and td, and between te and tf, the A/Dconverters 204R, 204G, 204B, 219R, 219G and 219B, and the shiftregisters 205R, 205G, 205B, 220R, 220G and 220B perform the abovedescribed operation. Through the above process, the shift register 205Routputs signal values r1, r2 and r3; the shift register 205G outputssignal values g1, g2 and g3; and the shift register 205B outputs signalvalues b1, b2 and b3. Similarly, the shift register 220R outputs signalvalue Fr1, Fr2 and Fr3; the shift register 220G outputs signal valuesFg1, Fg2 and Fg3; and the shift register 220B outputs signal values Fb1,Fb2 and Fb3. From among the three received signal values, each of thesignal switching devices 206R, 206G and 206B selects two signal values,each of which may correspond to a signal value selected by anotherswitching device. Likewise, each of the signal switching devices 221R,221G and 221B selects one signal value from among three received signalvalues. In this embodiment, it is assumed that the signal switchingdevice 221R selects signal value Fr1, the signal switching device 221Gselects signal value Fg2, and the signal switching device 221B selectssignal value Fb3.

In synchronization with signal φ3, which is supplied by the timinggenerator 203, the flip-flops 207A, 207B and 207C maintain, from timetg, signal values that are received from the signal switching devices206R, 206G and 206B, and output them. In this embodiment, assume thatthe flip-flops 207A, 207B and 207C hold the respective signal values r1,g2 and b3, and output them. Further, in synchronization with signal φ3,which is supplied by the timing generator 203, the flip-flops 222A, 222Band 222C maintain, from time tg, signal values that are received fromthe signal switching devices 206R, 206G and 206B, and signal values thatare received from the signal switching devices 221R, 221G and 221B, andoutput them. In this embodiment, in consonance with the aboveassumption, the flip-flop 222A holds and outputs signal values r1 andFr1; the flip-flop 222B holds and outputs signal values g2 and Fg2; andthe flip-flop 222C holds and outputs signal values b3 and Fb3. Thesubtracter 209A calculates absolute difference |r1-g2| between thesignal values that are output from the flip-flops 207A and 207B; and thesubtracter 209B calculates absolute difference |g2-b3| between thesignal values that are output from the flip-flops 207B and 207C. Thecomparator 211A compares the output of the subtracter 209A and thresholdvalue Th of the ROM 210, and outputs the result as a "true" or "false"binary signal. When the signal value output from the subtracter209A>threshold value Th, a "true" signal is output. In other cases, a"false" signal is output. Similarly, the comparator 211B compares theoutput of the subtracter 209B and threshold value Th of the ROM 210, andoutputs the result as a "true" or "false" binary signal. A logicarithmetic unit 223 calculates a logical sum for the signals that areprovided by the comparators 211A and 211B, and outputs the result. Whenone of the results provided by the comparators 211A and 211B is "true",the output of the logic-arithmetic unit 223 is "true".

At time th, the output of the logic-arithmetic unit 223 is held in theflip-flop 207G in synchronization with control signal φ4, and is output.

At times ti, tk and tm, in consonance with a "true" signal or a "false"signal from the flip-flop 207G, the signal switching device 213 selectsa set of the input terminals a1, b1 and c1 of the signal switchingdevice 213, or a set of the input terminals a2, b2 and c2. That is, whenthe output of the flip-flop 207G is "true", the signal switching device213 selects the input terminals a2, b2 and c2 and sequentially outputsthe signal values from the terminals in synchronization with signal φ6,which is supplied by the timing generator 212. When the output of theflip-flop 207G is "false", the signal switching device 213 selects theinput terminals a1, b1 and c1, and sequentially outputs signal values insynchronization with signal φ6, which is supplied by the timinggenerator 212. Assume that the output of the flip-flop 207G is "true"and that signal value r1 input to the input terminal al of the signalswitching device 213 and signal value Fr1 is input to the input terminala2. In other words, suppose that the signal value output by thesubtracter>threshold Th is established. Then, at time ti, signal valueFr1, which is input at the input terminal a2 of the signal switchingdevice 213, is sent to the output terminal O.

At time tj, in response to signal φ7 from the timing generator 212, theFIFO memory 214 stores signal value r1 that is output by the signalswitching device 213.

At time tk, in synchronization with signal φ6, the signal switchingdevice 213 selects the input terminal b2 from among the two inputterminals, b1 and b2, of the signal switching device 213. Since signalvalue Fg2 is input at the input terminal b2, the signal switching device213 forwards the signal value Fg2 to the output terminal O. In themanner as previously described, at time tk, the FIFO 214 outputs signalvalue Fr1, which was stored at time tj, and maintains the output signalvalue until time to. The output signal value passes through the terminal215 and is displayed on the liquid crystal panel 217.

At time t1, in response to signal φ7 from the timing generator 212, theFIFO memory 214 stores signal value Fg2, which is output by the signalswitching device 213.

At time tm, in synchronization with signal φ6, the signal switchingdevice 213 selects the input terminal c2 from among the two inputterminals, c1 and c2, of the signal switching device 213. Since signalvalue Fb3 is input at the input terminal b2, the signal switching device213 forwards the signal value Fb3 to the output terminal O.

At time tn, in response to signal φ7 from the timing generator 212, theFIFO memory 214 stores signal value Fb3, which is output by the signalswitching device 213 (the signal value that was selected at time tm).

At time to, the FIFO 214 outputs signal value g2, which was stored attime t1, and maintains the output signal value until time tp. The outputsignal value is displayed on the liquid crystal panel 217.

At time tp, the FIFO 214 outputs signal value g2, which was stored attime tn. The output signal value is displayed on the liquid crystalpanel 217.

The above described process is repeated during cycle PT. Therelationship between time T and PT is PT=3T.

In this embodiment, an input image signal is greatly varied during aunit of time, and when the degree of its change exceeds a predeterminedvalue, an image signal that is to be output to the liquid crystal panel217 is partially switched. When the signal filters 218R, 218G and 218Bare low-pass filters, filtering can be selectively performed in a regionwithin a received image in which moire tends to appear. Therefore,processing for reducing moire can be performed while information carriedby the input image signal is maintained.

As is described above, according to the display device of the presentinvention, at times t1, t2 and t3 (t1<t2<t3), sampling of signals isperformed for controlling red, green and blue display pixels; and signalvalues rn1, rn2 and rn3; gn1, gn2 and gn3 ; and bn1, bn2 and bn3 areacquired. When a signal value is selected from these signal values andis provided for three red, green, and blue pixels that are sequentiallyarranged, a difference between rn1 and rn2, a difference between gn1 andgn2, or a difference between bn1 and bn2 is compared with apredetermined threshold value Th. When each difference>Th, a signalvalue that is to be provided for the display pixels is switched. In thismanner, color moire in an image can be reduced, and information carriedby an input image signal can be satisfactorily displayed.

Further, a signal value that is to be provided to a pixel array in thedisplay device is switched in consonance with the change in theamplitude of an input image signal. At this time, when either a signalvalue obtained by performing predetermined filtering of an input signal,or a signal value of an input image signal obtained without filtering,is switched, signal filtering can be selectively performed only for aregion of an input image in which color moire tends to appear, andinformation carried by the input image signal can be effectivelyutilized.

Fifth Embodiment!

FIG. 9 is a block diagram illustrating the arrangement of a displaydevice according to a fifth embodiment of the present invention, andFIG. 10 is a block diagram illustrating a liquid crystal panel that isconnected to the display device shown in FIG. 9. In FIG. 9, imagesignals SR, SG and SB for controlling the luminance of red, green andblue display pixels are input at respective image input terminals 301R,301G and 301B. A/D converters 302A, 302B and 302C each sample and holdthe input image signals SR, SG and SB and convert them into digitalsignal values. The signal values are held until the following signalsare input. Sampling is performed in synchronization with signal φ1,which is supplied by a timing generator that will be described later.Shift registers 303A, 303B and 303C sequentially store three signalvalues that are output at a predetermined time interval by therespective A/D converters 302A, 302B and 302C, and output them at theiroutput terminals at the same time. From these three output terminals areacquired values that are obtained by sampling the input image signals atdifferent times. The shift operation is performed in synchronizationwith signal φ2, which is supplied by a timing generator. Flip-flops 304Athrough 304E each store an input signal in synchronization with signalφ3, which is supplied from a timing generator. Memories 305A and 305Bare used in which a predetermined signal value L0 is stored. Comparators306A and 306B compare respectively the signals in the memories 305A and306A with signals input to the flip-flops 304B and 304C, and output asignal of "1" or "0" as a result of each comparison. Subtracters 307Aand 307B calculate and output, as absolute values, a difference betweena signal to the flip-flop 304B and a signal to the flip-flop 304C, and adifference between a signal input to the flip-flop 304C and a signalinput to the flip-flop 304D. Memories 308A and 308B are employed inwhich a predetermined value D0 is stored. Comparators 309A and 309Bcompare respectively the signal values in the memories 308A and 308Bwith the signal values output by the subtracters 307A and 307B.Logic-arithmetic units 310A and 310B calculate and output a logicalproduct of signal values that are output by the comparators 306A and309A, and by the comparators 306B and 309B. Signal switching devices211A and 311B each select one of two input signals by using a receivedcontrol signal, and output the selected signal. Flip-flops 312A, 312Band 312C hold input signals in synchronization with signal φ4, which issupplied by a timing generator. A clock generator 313 supplies a signalto a timing generator. A timing generator 314 employs a signal receivedfrom the clock generator 313 to generate and output a timing clock thatis to be transmitted to the individual sections of the display device. Asignal switching device 315 selects one signal from input signals a, band c by using a control signal that is received from the timinggenerator 314. Input a is selected at the rise of the waveform ofcontrol signal φ5, input b is selected at the rise of the waveform ofcontrol signal φ6, and input c is selected at the rise of the waveformof control signal φ7. FIG. 11 is a diagram showing waveforms for controlsignals φ5, φ6 and φ7. An FIFO memory 316 is used, in which input signalvalues are sequentially stored in synchronization with control signal 48that is supplied by the timing generator 314, and from which the signalvalues are sequentially output in synchronization with control signalφ9. In synchronization with control signal φ5, the contents of the FIFOmemory 316 are reset. Reference number 317A denotes an output terminalof the FIFO memory 316, and 317B, an output terminal of the clockgenerator 313. These terminals are the same as the terminals 317A and317B in FIG. 10.

In FIG. 10, a timing generator 318 generates a timing clock by using aclock that is supplied to the terminal 317B by the clock generator 313.A D/A converter 319 converts a signal output by the FIFO memory 316 intoan analog signal. The signal obtained by conversion is transmitted to arow electrode driving circuit 321 in the liquid crystal panel 320. Theliquid crystal panel 320 includes the timing generator 318 and the D/Aconverter 319.

FIG. 11 is a timing chart showing a time-transient change for controlsignals φ1 through 9, which are transmitted from the timing generator314 in FIG. 9.

First, at time ta, upon receipt of signal φ1 from the timing generator314, each of the A/D converters 302A, 302B and 302C sample signals thatare input at the respective terminals 301R, 301G and 301B, and hold theresultant signals. These signals that are obtained by samplingcorrespond to signal values r1, g1 and b1 in FIG. 35.

At time tb, upon receipt of signal φ2 from the timing generator 314, theshift registers 303A, 303B and 303C respectively store and shift signalsthat are output by the A/D converters 302A, 302B and 302C.

During the periods between times td and tf, and between tg and ti, theA/D converters 302A, 302B and 302C, and the shift registers 303A, 303Band 303C perform the above described operation. Through this process,the shift register 303A transmits signal values r1, r2 and r3 to theflip-flop 304A; the shift register 303B transmits signal values g1, g2and g3 to the flip-flops 304B through 304D; and the shift register 303Ctransmits signal values b1, b2 and b3 to the flip-flop 304E.

At time ti, in synchronization with signal φ3, which is supplied by thetiming generator 314, the flip-flops 304A through 304E hold and outputsignal values that are output by the shift registers 303A, 303B and303C. In this embodiment, the flip-flops 304A, 304B, 304C, 304D and 304Ehold the respective signal values r1, g1, g2, g3 and b3. The comparator306A compares signal value g1 of the flip-flop 304B with signal value L0in the memory 305A, and outputs the result. When signal value g1 of theflip-flop 304B<L0, the comparator 306A outputs a signal of "1". Whensuch a condition is not established, the comparator 306A outputs asignal of "0". The comparator 306B compares signal value g2 of theflip-flop 304C with signal value L0 the memory 305B. When signal valueg2 of the flip-flop 304C<L0, the comparator 306B outputs a signal of"1". When such a condition is not established, the comparator 306Aoutputs a signal of "0". The subtracter 307A calculates as an absolutevalue a difference between signal value g1 of the flip-flop 304B andsignal value g2 of the flip-flop 304C, and outputs the absolute value.The subtracter 307B calculates as an absolute value a difference betweensignal value g2 of the flip-flop 304C and signal value g3 of theflip-flop 304D, and outputs the absolute value. The comparator 309Acompares signal value |g1-g2| of the subtracter 307A with signal valueD0 in the memory 308A, and outputs the result. When signal value |g1-g2|of the subtracter 307A>D0, the comparator 309A outputs a signal of "1".When such a condition is not established, the comparator 309A outputs asignal of "0". The comparator 309B compares signal value |g2-g3| of thesubtracter 307B with signal value D0 in the memory 308B, and outputs theresult. When signal value |g2-g3| of the subtracter 307B>D0, thecomparator 309B outputs a signal of "1". When such a condition is notestablished, the comparator 309B outputs a signal of "0". Thelogic-arithmetic unit 310A calculates a logical product of the output ofthe comparator 306A and the output of the comparator 309A, and outputs asignal of "1" or "0". The logic-arithmetic unit 310B calculates alogical product of the output of the comparator 306B and the output ofthe comparator 309B, and outputs a signal of "1" or "0". In consonancewith the output of the logic-arithmetic unit 310A, the signal switchingdevice 311A selects signal value r1 output by the flip-flop 304A orsignal value g2 output by the flip-flop 304C, and outputs the selectedsignal value. In consonance with the output of the logic-arithmetic unit310B, the signal switching device 311B selects signal value b3 output bythe flip-flop 304E or signal value g2 output by the flip-flop 304C, andoutputs the selected signal value.

At time tj, the flop-flops 312A, 312B and 312C store input signals insynchronization with signal φ4, which is supplied by the timinggenerator 314. The flip-flop 312A stores the output of the signalswitching device 311A, the flip-flop 312B stores the output of theflip-flop 304C, and the flip-flop 312C stores the output of the signalswitching device 311B.

At time tk, in synchronization with signal φ5, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input by the flip-flop 312A. At the sametime, at time tk, the FIFO memory 16 is reset in synchronization withsignal φ5 that is supplied by the timing generator 314.

At time t1, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedby the timing generator 314. At this time, the signal value output bythe flip-flop 312A is stored.

At time tm, in synchronization with signal φ6, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input from the flip-flop 312B. At thesame time, at time tm, the contents that were stored at time t1 areoutput from the FIFO memory 316 in synchronization with signal φ9, whichis supplied by the timing generator 314.

At time tn, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedby the timing generator 314. At this time, the signal value output bythe flip-flop 312B is stored.

At time to, in synchronization with signal φ7, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input by the flip-flop 312C.

At time tp, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedby the timing generator 314. At this time, the signal value output fromthe flip-flop 312C is stored. At the same time, at time tp, the contentsthat were stored at time tn are output by the FIFO memory 316 insynchronization with signal φ9, which is supplied by the timinggenerator 314.

At time tq, the contents that were stored at time tp are output by theFIFO memory 316 in synchronization with signal φ9, which is supplied bythe timing generator 314. The output of the FIFO memory 316 istransmitted through the terminal 317A and is displayed on the liquidcrystal panel 320.

The above described process is repeated during cycle PT. Therelationship between time T and PT is PT=3T.

Sixth Embodiment!

FIG. 12 is a block diagram illustrating the arrangement of a displaydevice according to a sixth embodiment of the present invention. FIG. 13is a diagram showing an input-output characteristic example for a signalprocessing circuit in FIG. 12, which will be described later. The samereference numbers as are used in FIG. 9 are also used in FIG. 12 todenote corresponding or identical components. The operating timing isalso the same as that in FIG. 11. Signal processors 321A and 321B inFIG. 12 have the relationship Y=f(X) shown in FIG. 13 for input signal Xand output signal Y. The input signal X denotes any integer from 0 toXm, and the output signal Y denotes any integer from 0 to Ym.

First, at time ta, upon receipt of signal φ1 from the timing generator314, the A/D converters 302A, 302B and 302C each sample signals that areinput at the respective terminals 301R, 301G and 301B, and hold theresultant signals. These signals that are obtained by samplingcorrespond to signal values r1, g1 and b1.

At time tb, upon receipt of signal φ2 from the timing generator 314, theshift registers 303A, 303B and 303C store and shift signals that areoutput by the A/D converters 302A, 302B and 302C, respectively.

During the periods between times td and tf, and between tg and ti, theA/D converters 302A, 302B and 302C, and the shift registers 303A, 303Band 303C perform the above described operation. Through this process,the shift register 303A outputs signal values r1, r2 and r3; the shiftregister 303B outputs signal values g1, g2 and g3; and the shiftregister 303C outputs signal values b1, b2 and b3.

At time ti, in synchronization with signal φ3, which is supplied by thetiming generator 314, the flip-flops 304A through 304E hold and outputsignal values that are output from the shift registers 303A, 303B and303C. In this embodiment, the flip-flops 304A, 304B, 304C, 304D and 304Ehold the respective signal values r1, g1, g2, g3 and b3. The subtracter307A calculates as an absolute value a difference between signal valueg1 of the flip-flop 304B and signal value g2 of the flip-flop 304C, andoutputs the absolute value. The subtracter 307B calculates as anabsolute value a difference between signal value g2 of the flip-flop304C and signal value g3 of the flip-flop 304D, and outputs the absolutevalue. The signal processor 321A receives signal value g1 from theflip-flop 304B and outputs signal value f(g1). The signal processor 321Breceives signal value g2from the flip-flop 304C and outputs signal valuef(g2). The comparator 309A compares signal value |g1-g2| of thesubtracter 307A with signal value f(g1) of the signal processor 321A.When |g1-g2|>f(g1), the comparator 309A outputs a signal of "1". Whensuch a condition is not established, the comparator 309A outputs asignal of "0". The comparator 309B compares signal value |g2-g3| of thesubtracter 307B with f(g2) of the signal processor 321B. When|g2-g3|>f(g2), the comparator 309B outputs a signal of "1". When such acondition is not established, the comparator 309B outputs a signal of"0". In consonance with the output of the comparator 309A, the signalswitching device 311A selects either signal value r1 of the flip-flop304A or signal value g2 of the flip-flop 304C, and outputs the selectedsignal value. In consonance with the output of the comparator 309B, thesignal switching device 311B selects either signal value b3 output bythe flip-flop 304E or signal value g2 output by the flip-flop 304C, andoutputs the selected signal value.

At time tj, the flop-flops 312A, 312B and 312C store input signals insynchronization with signal φ4 that is supplied from the timinggenerator 314. The flip-flop 312A stores the output of the signalswitching device 311A, the flip-flop 312B stores the output of theflip-flop 304C, and the flip-flop 312C stores the output of the signalswitching device 311B.

At time tk, in synchronization with signal φ5, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input from the flip-flop 312A. At thesame time, at time tk, the FIFO memory 316 is reset in synchronizationwith signal 45, which is supplied by the timing generator 314.

At time t1, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedby the timing generator 314. At this time, the signal value output bythe flip-flop 312A is stored.

At time tm, in synchronization with signal φ6, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input by the flip-flop 312B. At the sametime, at time tm, the contents that were stored at time t1 are outputfrom the FIFO memory 316 in synchronization with signal φ9, which issupplied by the timing generator 314.

At time tn, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedfrom the timing generator 314. At this time, the signal value output bythe flip-flop 312B is stored.

At time to, in synchronization with signal φ7, which is supplied by thetiming generator 314, the signal switching device 315 outputs to theFIFO memory 316 a signal value input by the flip-flop 312C.

At time tp, the output of the signal switching device 315 is stored inthe FIFO memory 316 in synchronization with signal φ8, which is suppliedby the timing generator 314. At this time, the signal value output fromthe flip-flop 312C is stored. At the same time, at time tp, the contentsthat were stored at time tn are output by the FIFO memory 316 insynchronization with signal φ9, which is supplied by the timinggenerator 314.

At time tq, the contents that were stored at time tp are output by theFIFO memory 316 in synchronization with signal φ9, which is supplied bythe timing generator 314. The output of the FIFO memory 316 istransmitted through the terminal 317A and is displayed on the liquidcrystal panel 320.

The above described process is repeated during cycle PT. Therelationship between time T and PT is PT=3T.

As is described above, according to the fifth and the sixth embodimentof the present invention, a display device, comprises: detection meansfor detecting a change value |A-B| between continuous signal values Aand B that are acquired by sampling; first comparison means forcomparing the signal value A with predetermined value L0; secondcomparison means for comparing the change value |A-B| with predeterminedvalue D0; and replacement means for, in consonance with results ofcomparisons by the first and second comparison means, replacing a signalvalue, which is to be provided for a pixel of a specific color, with asignal value for another color. Therefore, moire for an image signal canbe reduced and information carried by the image signal can beeffectively utilized and displayed.

Seventh Embodiment!

FIG. 14 is a block diagram illustrating a liquid crystal display deviceaccording to a seventh embodiment of the present invention. Referencenumber 401 denotes an input terminal for an image signal; 402, a signalprocessing circuit; 403, a synchronizing separation circuit; 404, acontroller; 405, an X-driver; 406, a Y-driver; 407, an LCD; 408, aninput terminal for a control signal for displaying characterinformation; 409, a character generation circuit for generatingcharacter information to be displayed based on a control signal that isinput at the input terminal 408; and 410, a synthesizing circuit forsynthesizing an image signal and character information. The LCD 407 hasthe arrangement shown in FIG. 31. The X-driver 405 is a shift registerhaving the structure shown in FIG. 15. In FIG. 15, reference number 421denotes an input terminal for a start pulse; 422, an input terminal fora drive pulse; 423, a D-flip-flop; 424, an output terminal for a drivepulse; 425, an input terminal for a mode select signal; and 426, aswitching circuit.

The operation of a liquid crystal display device according to theseventh embodiment of the present invention will now be described whilereferring to FIGS. 14 and 15. The signal processing circuit 402 performsa predetermined process, such as γ compensation or inversion, on animage signal that is input at the input terminal 401 in order to displaythe image signal. The processed signal is transmitted to thesynthesizing circuit 410, and also to the synchronizing separationcircuit 403, which separates a synchronization signal from the receivedsignal. The separated synchronization signal is transmitted to thecontroller 404. In response to the signal, the controller 404 supplies,to the X-driver 405 and the Y-driver 406, a predetermined drive pulse,for driving the LCD 407, that is synchronized with an image signal.Further, a control signal, to display character information togetherwith an image on the LCD 407, is input at the input terminal 408 and istransmitted to the character generation circuit 409. The synchronizationsignal that was separated by the synchronizing separation circuit 403 isalso transmitted to the character generation circuit 409. The charactergeneration circuit 409 then generates characters to be displayed on theLCD 407 in synchronization with an image signal. The image signal outputby the signal processing circuit 402 and the output of the charactergeneration circuit 409 are synthesized by the synthesizing circuit 410,and the result is supplied to the X-driver 405. The LCD 407 is driven byan image signal, a signal with which character information issynthesized and a drive pulse, all of which are supplied by the X-driver405, and by a drive pulse that is supplied by the Y-driver 406, andcharacter information is displayed on the LCD 407 together with an imageat the same time.

In addition, the character generation circuit 409 supplies to the inputterminal of the X-driver 405 a mode select signal for changing a drivemode. More specifically, the character generation circuit 409 connectsthe switching circuit 426 across side a for a region in which charactersare displayed on a screen, and connects the switching circuit 426 acrossside b for an region in which characters are not displayed. At thistime, m output terminals 424 are connected respectively to switchingelements 465R, 465G and 465B of the LCD shown in FIG. 31 via m inputterminals 467R, 467G and 467B. When a start pulse is input at the inputterminal 421 at the beginning of a horizontal scan period, and a clockthat is m times a horizonal frequency is input at the input terminal422, an m-stage shift register in FIG. 15 is driven by the drive pulse.At this time, for a region in which characters are displayed, uponreceipt of a control signal from the character generation circuit 409,the switching circuit 426 is connected across side a. Therefore, thesame drive pulse is output to every three of the output terminals 424.The drive pulse is supplied to the gates of the switching elements 465R,465G and 465B via the input terminals 467R, 467G and 467B, and all theswitches are turned on. As a result, sampling is performed at the sametime for image signals that are input at input terminals 464R, 464G and464B, and the resultant signals are supplied to vertical signal lines.For a region in which characters are not displayed, the switchingcircuit 426 is connected across side b in consonance with a controlsignal from the character generation circuit 409. Therefore, differentdrive pulses are sequentially sent from the output terminals 424 to thegates of the switching elements 465R, 465G and 465B, and the switchesare turned on. As a result, sampling is performed at different timingsfor image signals that are input at the input terminals 464R, 464G and464B, and the resultant signals are supplied to a vertical signal line.

The operation performed hereinafter is common to the above two modes. Inthe Y-driver in FIG. 33B, when a start pulse is input at the inputterminal 431 at the beginning of a vertical scan period, and a horizonalfrequency clock is input at the input terminal 432, the shift registerhaving n stages is driven by the drive pulse, and the output pulse ofthe shift register is output to the output terminals 434. Each of theoutput terminals 434 is connected to the input terminal 468. When adrive pulse that is output by the Y-driver 406 is supplied to the gateof the switching device 461 across a predetermined horizontal gate line,and each switch is turned on, the liquid crystal cell 462 and thecapacitor 463 hold electric charges that correspond to potentialdifferences between signals that are supplied to the input terminals464, and a voltage that is applied to the common electrode 466. At thistime, a predetermined voltage is provided for the common electrode 466.The above process is repeated and an image for one screen can bedisplayed on the LCD.

In a liquid crystal display device, with this arrangement, which addscharacter information to an input image for a display, for a region inwhich characters are not displayed sampling is performed at differentphases of image signals relative to R, G and B pixels. For a region inwhich characters are displayed sampling is performed at the same phasefor R, G and B pixels. As a result, the resolution in a region in whichan image is displayed is increased, and an occurrence of foldeddistortion can be prevented when characters are to be displayed.

Eighth Embodiment!

FIG. 16 is a block diagram illustrating a liquid crystal display deviceaccording to an eighth embodiment of the present invention. Referencenumber 411 denotes a delay circuit for an image signal. An X-driver 405is the same as that shown in FIG. 33A. The other components are denotedby using the same reference numbers as are used in FIG. 14. FIG. 17 is adiagram illustrating one example of the delay circuit 411 in FIG. 16.Reference numbers 441R, 441G and 441B denote input terminals for imagesignals; 442R and 442G, switching circuits; 423, a delay circuit; 444Rand 444G, switching circuits; 445, an input terminal for a mode selectsignal; and 446R, 446G and 446B, output terminals for image signals.

The operation of a liquid crystal display device according to the eighthembodiment of the present invention will now be described whilereferring to FIGS. 16 and 17. The signal processing circuit 402 performsa predetermined process on an image signal that is input at the inputterminal 401 in order to display the image signal. The processed signalis transmitted to the synthesizing circuit 410, and also to thesynchronizing separation circuit 403, which separates a synchronizationsignal from the received signal. The separated synchronization signal istransmitted to the controller 404. In response to the signal, thecontroller 404 supplies, to the X-driver 405 and the Y-driver 406, apredetermined drive pulse, for driving the LCD 407, that is synchronizedwith an image signal. Further, a control signal, to display characterinformation together with an image on the LCD 407, is input at the inputterminal 408 and is transmitted to the character generation circuit 409.The synchronization signal that was separated by the synchronizingseparation circuit 403 is also transmitted to the character generationcircuit 409. The character generation circuit 409 then generatescharacters to be displayed on the LCD 407 in synchronization with animage signal. The image signal output by the signal processing circuit402 and the output of the character generation circuit 409 aresynthesized by the synthesizing circuit 410, and the result is suppliedacross the delay circuit 411 to the X-driver 405. The LCD 407 is drivenby an image signal, a signal with which character information issynthesized and a drive pulse, all of which are supplied by the X-driver405, and a drive pulse that is supplied by the Y-driver 406, andcharacter information is displayed on the LCD 407 with an image at thesame time.

In addition, the character generation circuit 409 supplies to the inputterminal of the X-driver 405 a mode select signal for changing a drivemode. More specifically, the character generation circuit 409 connectsthe switching circuits 442R, 442G, 444R and 444G across side a for aregion in which characters are displayed on a screen, and connects theswitching circuits 442R, 442G, 444R and 444G across side b for a regionin which characters are not displayed. The delay circuit 443 provides adelay that is equivalent to one pixel of the LCD 407. Thus, when theswitching circuits 442R, 442G, 444R and 444G are connected across sidea, image signal GOUT, which is output at the output terminal 446G, isdelayed by one pixel relative to image signal BOUT, which is output atthe output terminal 446B, and signal ROUT, which is output at the outputterminal 446R, is delayed by two pixels relative to signal BOUT. Whenthe switching circuits 442R, 442G, 444R and 444G are connected acrossside b, signals that are input at the input terminals 441R, 441G and441B are sent unchanged to the output terminals 446R, 446G and 446B.

In this embodiment, since the X-driver 405 shown in FIG. 33A isemployed, in the LCD 407 sampling is performed for R, G and B pixels atthe same phase. However, when an image signal passes through the delaycircuit 411, a delay process is performed for the image signal in aregion in which characters are not displayed, so that the same effect asis obtained bysampling R, G and B pixels at different phases isacquired. Further, since an image signal for a region in whichcharacters are not displayed does not pass through the delay circuit 411and thus a delay process is not performed for that signal, sampling isperformed for R, G and B pixels at the same phase. The operationhereinafter is the same as that in the seventh embodiment, and nofurther explanation will be given.

As is described above, for a region of a liquid crystal display devicewhich adds character information to an input image for a display, aconventional x-driver is applied, and as in the seventh embodiment, inwhich characters are not displayed, sampling for image signals relativeto R, G and B pixels is performed at different phases. For a region inwhich characters are displayed, sampling is performed at the same phasefor R, G and B pixels. As a result, the resolution in a region in whichan image is displayed is increased, and an occurrence of foldeddistortion can be prevented when characters are to be displayed.

As a modification of this embodiment, the delay circuit 411 in FIG. 16may have the arrangement shown in FIG. 18. Reference numbers 451R, 451Gand 451B denote input terminals for image signals; 452, a sample-holdcircuit; and 453R, 453G and 453B, output terminals for image signals.For a region in which characters are not displayed, the controller 404transmits to the delay circuit 411 sample-hold pulses shown in FIG. 19A.The phase of each pulse is shifted by one pixel of the LCD. Thus, in thedelay circuit shown in FIG. 17, image signal GOUT, which is output atthe output terminal 453G, is delayed by one pixel relative to signalBOUT, which is output at the output terminal 453B, and signal ROUT,which is output at the output terminal 453R, is delayed by two pixels.For a region in which characters are displayed, pulses shown in FIG. 19Bare supplied. By making the sample-hold circuits 452 pass signalsthrough, image signals that are input at the input terminals 451R, 451Gand 451B are output unchanged to the output terminals 453R, 453G and453B.

With this arrangement, the same effect as is obtained when the delaycircuit in FIG. 17 is employed is acquired. Further, since the delaycircuit is designed with sample-hold circuits, this arrangement caneasily cope with a change in the number of pixels in the LCD.

Ninth Embodiment!

The arrangement for a liquid crystal display device according to a ninthembodiment of the present invention is the same as that shown in FIG. 16for the eighth embodiment, except that the X-driver 405 in FIG. 34 andthe delay circuit 411 in FIG. 20 are employed. The operation for theninth embodiment is also the same as that for the eighth embodiment,except for the control of these components, and no explanation for itwill be given. The same reference numbers as are used in FIG. 17 arealso used in FIG. 20 to denote corresponding or identical components.For a region in which characters are displayed, switching circuits 442B,442G, 444B and 444G are connected across side a in consonance with acontrol signal from a character generation circuit 409. For a region inwhich characters are not displayed, these switching circuits areconnected across side b. Since the X-driver 405 is designed as is shownin FIG. 34, an LCD 407 performs sampling for R, G and B pixels atdifferent timings. Since a delay process is not performed for an imagesignal for a region in which characters are not displayed, sampling isperformed for R, G and B pixels at different phases. Since an imagesignal for a region in which characters are displayed passes through thedelay circuit 411 and thus a delay process is performed for that signal,the same effect as is obtained by sampling the three pixels at the samephase can be acquired.

In this manner, the effect obtained in the eighth embodiment can also beacquired in this embodiment.

As well as in the eighth embodiment, the delay circuit 411 shown in FIG.21 may be employed, and sample-hold pulses shown in FIGS. 22A and 22Bmay be supplied. In FIG. 21, the same reference numbers as are used inFIG. 18 are also used to denote corresponding or identical components.In addition, sample-hold pulses in FIG. 22A can be supplied for a regionin which characters are not displayed, and pulses in FIG. 22B can besupplied for a region in which characters are displayed.

Tenth Embodiment!

FIG. 23 is a block diagram illustrating a liquid crystal display deviceaccording to a tenth embodiment of the present invention. A characterregion discrimination circuit 412 identifies a character region for aninput image signal. The other components are the same as those shown inFIG. 14.

The operation of the liquid crystal display device according to thetenth embodiment of the present invention will now be described whilereferring to FIG. 23. An image signal that is input at an input terminal401 is transmitted to a signal processing circuit 402, a synchronizingseparation circuit 403, and a character region discrimination circuit412. The signal processing circuit 402 performs a predetermined processon the image signal that is to be displayed on an LCD 407, and transmitsthe resultant image signal to an X-driver 405. The synchronizingseparation circuit 403 separates a synchronization signal from the imagesignal, and transmits the synchronization signal to a controller 404.Upon receipt of this signal, the controller 404 supplies predetermineddrive pulses to an X-driver 405 and a Y-driver 406 to drive the LCD 407in synchronization with the image signal. The character regiondiscrimination circuit 412 identifies, from an input image signal, aregion in which characters are included and a region in which charactersare not included, and supplies a control signal for drive mode switchingto the X-driver 405. The LCD 407 is driven by an image signal and adrive pulse that is supplied by the X-driver 405 and by a drive pulsethat is supplied by the Y-driver 406, and displays character informationwith an image on a screen.

In this embodiment, the X-driver 405 is the same as that shown in FIG.15. When, as well as in the seventh embodiment, the character regiondiscrimination circuit 412 identifies a region in which characters areincluded, the character region discrimination circuit 412 outputs acontrol signal, and the switching circuit 426 is connected across sidea. When the circuit 412 ascertains that no characters are included in aregion, the switching circuit 426 is connected across side b. Therefore,as in the seventh embodiment, when an input image signal is to bedisplayed on the LCD 407, sampling of R, G and B pixels is performed atdifferent phases for a region in which no characters are included, whilesampling of R, G and B pixels is performed at the same phase for aregion in which characters are included. The operation hereinafter isthe same as that in the seventh embodiment, and no further explanationwill be given.

As is described above, for a region, of a liquid crystal display devicethat displays an input image in which character information is included,in which characters are not displayed, sampling of image signalsrelative to R, G and B pixels is performed at different phases, and fora region in which characters are displayed sampling of R, G and B pixelsis performed at the same phase. As a result, the resolution in a regionin which an image is displayed is increased, and an occurrence of foldeddistortion can be prevented when characters are to be displayed.

Eleventh Embodiment!

FIG. 24 is a block diagram illustrating a liquid crystal display deviceaccording to an eleventh embodiment of the present invention. In thisembodiment, the X-driver 405 shown in FIG. 33A is employed, and thedelay circuit 411 shown in FIG. 17 or FIG. 18 is employed. The delaycircuit 411 is operated by using a control signal that is transmittedfrom a character region discrimination circuit 412 through a controller404, and that controls an image signal display. The control method isthe same as that described in the eighth embodiment; for a region inwhich characters are not displayed, a delay process is performed for animage signal, and for a region in which characters are displayed, thedelay process is not performed.

With this arrangement, while a conventional X-driver is applied, thesame effect as is acquired in the tenth embodiment can be obtained.

Twelfth Embodiment!

The arrangement of a liquid crystal display device according to atwelfth embodiment of the present invention is the same as that for theeleventh embodiment in FIG. 24. In this embodiment, the X-driver 405shown in FIG. 34 is employed, and the delay circuit 411 shown in FIG. 20or FIG. 21 is employed. The delay circuit 411 is operated by using acontrol signal that is transmitted from a character regiondiscrimination circuit 412 through a controller 404, and that controlsan image signal delay. The control method is the same as that describedin the ninth embodiment; for a region in which characters are notdisplayed, a delay process is not performed for an image signal, and fora region in which characters are displayed, the delay process isperformed.

With this arrangement, the same effect as is acquired in the eleventhembodiment can be obtained.

As is described above, according to the seventh through the twelfthembodiments of the present invention, for a region, of a liquid crystaldisplay device that adds character information to an input image signalfor a display, in which characters are not displayed sampling of imagesignals relative to R, G and B pixels is performed at different phases,and for a region in which characters are displayed sampling of R, G andB pixels is performed at the same phase. As a result, the resolution ofa region in which an image is displayed is increased, and an occurrenceof folded distortion can be prevented when characters are to bedisplayed.

In addition, when delay means is provided for a display device, whichadds character information to an input image signal for a display, aconventional X-driver can be applied without any modification.

Thirteenth Embodiment!

The arrangement of a liquid crystal display device according to athirteenth embodiment of the present invention is the same as is shownin FIG. 23. In FIG. 23, reference number 401 denotes an input terminalfor an image signal; 402, a signal processing circuit; 403, asynchronizing separation circuit; 404, a controller; 405, an X-driver;406, a Y-driver; 407, an LCD; and 412, a character region discriminationcircuit for identifying a character region for an input image signal.The LCD 407, as well as prior art, has the arrangement as is shown inFIG. 31. The X-driver 405 is a shift register with the structure shownin FIG. 15. Reference number 421 denotes an input terminal for a startpulse; 422, an input terminal for a drive pulse; 423, a D-flip-flop;424, an output terminal for a drive pulse; 425, an input terminal for amode select signal; and 426, a switching circuit. A Y-driver 406 alsohas the same structure as prior art and is shown in FIG. 33B.

The operation of a liquid crystal display device according to thethirteenth embodiment of the present invention will now be describedwhile referring to FIGS. 23 and 15. An image signal that is input at theinput terminal 401 is transmitted to the signal processing circuit 402,the synchronizing separation circuit 403 and the character regiondiscrimination circuit 412. The signal processing circuit 402 performs apredetermined process, such as γ compensation or inversion, on the imagesignal in order to display the image signal. The processed signal istransmitted to the X-driver 405. The synchronizing separation circuit403 separates a synchronization signal from the received signal and theseparated synchronization signal is transmitted to the controller 404.In response to the signal, the controller 404 supplies, to the X-driver405 and the Y-driver 406, a predetermined drive pulse, for driving theLCD 407, that is synchronized with an image signal. Further, thecharacter region discrimination circuit 412 identifies, from the inputimage signal, a region in which characters are included and a region inwhich characters are not included, and then supplies a control signalfor drive mode switching to the X-driver 405. The LCD 407 is driven byan image signal and a drive pulse that is supplied by the Y-driver 406,and character information and an image are displayed on the LCD 407 atthe same time.

The character region discrimination circuit 412 connects the switchingcircuit 426 across side a for a region in which characters are displayedon a screen, and connects the switching circuit 426 across side b for aregion in which characters are not displayed. At this time, m outputterminals 424 are connected respectively to switching elements 465R,465G and 465B of the LCD 407 via m input terminals 467R, 467G and 467B.When a start pulse is input from the input terminal 421 at the beginningof a horizontal scan period, and a clock that is m times a horizonalfrequency is input from the input terminal 422, an m-stage shiftregister in FIG. 15 is driven by the drive pulse. At this time, for aregion in which characters are displayed, upon receipt of a controlsignal from the character region discrimination circuit 412 theswitching circuit 426 is connected across side a. Therefore, the samedrive pulse is output to every three output terminals 424. The drivepulse is supplied to the gates of the switching elements 465R, 465G and465B via the input terminals 467R, 467G and 467B, and all the switchesare turned on. As a result, sampling is performed at the same time forimage signals that are input from input terminals 464R, 464G and 464B,and the resultant signals are supplied to vertical signal lines. For aregion in which characters are not displayed, the switching circuit 426is connected across side b in consonance with a control signal from thecharacter region discrimination circuit 412. Therefore, different drivepulses are sequentially sent from the output terminals 424 to the gatesof the switching elements 465R, 465G and 465B, and the switches areturned on. As a result, sampling of image signals that are input at theinput terminals 464R, 464G and 464B is performed at different timings,and the resultant signals are supplied to a vertical signal line.

The operation performed hereinafter is common to the above two modes.When a start pulse is input at the input terminal 431 at the beginningof a vertical scan period, and a horizonal frequency clock is input atthe input terminal 432, the shift register in the Y-driver having nstages is driven by the drive pulse, and the output pulse of the shiftregister is output to the output terminals 434. Each of the outputterminals 434 is connected to the input terminal 468. When a drive pulsethat is output by the Y-driver 406 is supplied to the gate of theswitching device 461 across a predetermined horizontal gate line, andeach switch is turned on, the liquid crystal cell 462 and the capacitor463 hold electric charges that correspond to potential differencesbetween signals that are supplied to the input terminals 464 and avoltage that is applied to the common electrode 466. At this time, apredetermined voltage is provided for the common electrode 466. Theabove process is repeated, and an image for one screen can be displayedon the LCD.

FIG. 25 is a specific diagram illustrating the arrangement of thecharacter region discrimination circuit 412 in FIG. 23 according to thethirteenth embodiment of the present invention. Reference number 411denotes an input terminal for a video signal; 412, a luminance signalproducing circuit; 413, a color signal producing circuit from an inputimage signal that produces a color signal; 414, a luminance signal leveldetection circuit; 415, a color level detection circuit; 416, adiscrimination circuit for determining whether a region is a region inwhich characters are displayed or a region in which characters are notdisplayed; and 417, an output terminal for a mode select signal.

The operation of the character region discrimination circuit in thisembodiment will now be described. An image signal that is supplied tothe input terminal 401 in FIG. 23, i.e., a signal that is to betransmitted to the LCD 407 via the signal processing circuit 402, isinput at the input terminal 411. The image signal that was input at theinput terminal 411 is transmitted to the luminance signal producingcircuit 412 and also to the color signal producing circuit 413. Theluminance signal producing circuit 412 produces a luminance signal froman image signal. In other words, when an input image signal is a compleximage signal, Y/C separation is performed to produce a luminance signal.When an input image signal is an RGB signal, a predetermined calculation(Y=0.3R+0.59G+0.11B) is performed to produce a luminance signal. Thecolor signal producing circuit 413 produces a color signal from an inputimage signal. When an input image signal is a complex image signal, aproduced color signal may be a chroma signal obtained by Y/C separation,or a color difference signal obtained by demodulating the chroma signal.When an input signal is an RGB signal, a predetermined calculation isperformed to produce a color difference signal. A luminance signal thatis produced by the luminance signal producing circuit 412, and a colorsignal that is produced by the color signal producing circuit 413 areinput to the luminance signal level detection circuit 414 and the colorsignal level detection circuit 415, respectively. The signal levels ofthe individual signals are determined and are sent to the discriminationcircuit 416. The discrimination circuit 416 determines whether or not areceived signal indicates a character, and transmits the result as amode select signal to the output terminal 417. The mode select signalthat is output at the output terminal 417 is supplied to the X-driver405 to control it, as is described above. More specifically, thediscrimination circuit 416 outputs a control signal, so that, for aregion in which characters are displayed on a screen, the switchingcircuit 426 is connected across side a, and for a region in whichcharacters are not displayed on a screen, the switching circuit 426 isconnected across side b.

A specific determination method performed by the discrimination circuit416 in this embodiment will now be explained. When the luminance signallevel detection circuit 414 determines that the level of a luminancesignal is higher than a predetermined value, and at that time the colorlevel detection circuit 415 does not detect a color signal, i.e., whenan input image is monotone, or when the color signal level detectioncircuit 415 determines the color signal level is lower than apredetermined value, i.e., when an input image is nearly monotone, thediscrimination circuit 416 ascertains that a region of a display imagethat is currently input is a region in which characters are included,and outputs an appropriate mode select signal. The discriminationcircuit 416 ascertains that the other regions are those in whichcharacters are not included, and outputs a corresponding mode selectsignal. As is described above, the discrimination circuit in thisembodiment ascertains that a region of a display image for which a colorsignal level is lower than a predetermined value is a region in whichcharacters are displayed, and that a region for which the color signallevel is greater than a predetermined value is a region in whichcharacters are not displayed. According to the results of thedetermination, the discrimination circuit 416 outputs a select signalfor controlling a phase for sampling before an image is to be displayed.

With this arrangement, for a region, of a liquid crystal display devicethat displays an input image in which character information is included,in which characters are not displayed, sampling of image signalsrelative to R, G and B pixels is performed at different phases, and fora region in which characters are displayed, sampling is performed at thesame phase for R, G and B pixels. As a result, the resolution in aregion in which an image is displayed is increased, and an occurrence offolded distortion can be prevented when characters are to be displayed.

Fourteenth Embodiment!

FIG. 26 is a diagram illustrating the arrangement of a character regiondiscrimination circuit that is employed for a liquid crystal displaydevice according to a fourteenth embodiment of the present invention.The general arrangement of the display device is the same as that in thethirteenth embodiment, and as it was previously shown in FIG. 23, noexplanation will be given. In FIG. 26, reference number 514b denotes aluminance signal level change detection circuit; 515b, a color signallevel change detection circuit; and 516b, a discrimination circuit fordetermining a region in which characters are to be displayed or a regionin which characters are not to be displayed.

The operation of the character region discrimination circuit and thedetermination method in this embodiment will be explained. An imagesignal that is input at an input terminal 511 is transmitted to aluminance signal producing circuit 512 and to a color signal producingcircuit 513, which then output a luminance signal and a color signal,respectively. These signals are supplied to the luminance signal levelchange detection circuit 514b and the color signal level changedetection circuit 515b. The luminance signal level change detectioncircuit 514b detects a change in the level of a received luminancesignal, and transmits the result of the detection to the discriminationcircuit 516b. In the same manner, the color signal level changedetection circuit 515b detects a change in the level of an input colorsignal, and transmits the result of the detection to the discriminationcircuit 516b. Specific arrangements of the luminance signal level changedetection circuit 514b and the color signal level change detectioncircuit 515b are shown in FIG. 27. As is shown in FIG. 27, a luminancesignal or a color signal that is input at the input terminal 5141 issent to an arithmetic operation circuit 5143 together with a signal thatis delayed a predetermined time by a delay circuit 5142. The arithmeticoperation circuit outputs the result of the arithmetic operation at theoutput terminal 5144. In other words, a difference at a given timeinterval between the signal levels of input luminance signal and theinput color signal is output as the result of the detection. Thediscrimination circuit 516b employs the received detection signals todetermine a region in which characters are displayed or a region inwhich characters are not displayed, and outputs the result of thedetermination to the output terminal 517. At this time, when adifference in the level of a luminance signal, which is supplied by theluminance signal level change detection circuit 514b, is greater than apredetermined value, and when a difference in the level of a colorsignal, which is supplied by the color signal level change detectioncircuit 515b, is smaller than a predetermined value, the discriminationcircuit 516b determines that the target portion is a region in whichcharacters are to be displayed, and outputs a corresponding mode selectsignal to the output terminal 517. In the other case, the discriminationcircuit 516b determines that a portion is a region in which charactersare not to be displayed, and outputs a corresponding mode select signalto the output terminal 517. As is described above, the discriminationcircuit in this embodiment ascertains that a portion of a display image,for which a change in a luminance signal level is greater than apredetermined value and a change in a color signal level is smaller thana predetermined value, is a region in which characters are displayed,and that the other region is a region in which characters are notdisplayed. According to the results of the determination, thediscrimination circuit 416 outputs a select signal for controlling aphase for sampling before an image is to be displayed.

Although, in this embodiment, the changes in the signal levels of aluminance signal and a color signal are detected, as is shown in FIG.28, frequency elements of a luminance signal and of a color signal maybe detected. More specifically, a luminance signal frequency detectioncircuit 514c detects frequency elements of a luminance signal that isproduced by the luminance signal producing circuit 512. Similarly, acolor signal frequency detection circuit 515c detects frequency elementsof a color signal that is produced by the color signal producing circuit513. The results of these detections are supplied to a discriminationcircuit 516c. When the frequency of the luminance signal that is sentfrom the luminance signal frequency detection circuit 514c is greaterthan a predetermined value, and when the frequency of the color signalthat is sent from the color signal frequency detection circuit 515c issmaller than a predetermined value, the discrimination circuit 516cdetermines that the target portion is a region in which characters areto be displayed, and outputs a corresponding mode select signal to theoutput terminal 517. In the other case, the discrimination circuit 516cdetermines that a target portion is a region in which characters are notdisplayed, and outputs a corresponding mode select switch to the outputterminal 517. As is described above, the discrimination circuit in thisembodiment ascertains that a portion of a display image, for which thefrequency of a luminance signal is greater than a predetermined valueand the frequency of a color signal is smaller than a predeterminedvalue, is a region in which characters are displayed, and that the otherregion is a region in which characters are not displayed. According tothe result of the determination, the discrimination circuit 416 outputsa select signal for controlling a phase for sampling before an image isto be displayed.

With this arrangement, for a region, of a liquid crystal display devicethat displays an input image in which character information is included,in which characters are not displayed, sampling of image signalsrelative to R, G and B pixels is performed at different phases, and fora region in which characters are displayed, sampling is performed for R,G and B pixels at the same phase. As a result, the resolution in aregion in which an image is displayed is increased, and an occurrence offolded distortion can be prevented when characters are to be displayed.

A combination of the discrimination circuits that are used in thethirteenth and fourteenth embodiments may select a display mode inconsonance with the results of determinations from a plurality ofdiscrimination circuits, i.e., the signal level change and the frequencychange.

Fifteenth Embodiment!

The arrangement of a liquid crystal display device according to afifteenth embodiment of the present invention is the same as that shownin FIG. 24. In FIG. 24, reference number 411 denotes a delay circuit foran image signal. An X-driver 405 is the same as that shown in FIG. 33A.As the arrangement of a character region discrimination circuit 408 isthe same as that in the thirteenth or fourteenth embodiment, anexplanation for it will not be given. The delay circuit 411 is the sameas that in FIG. 17. Reference numbers 441R, 441G and 441B denote inputterminals for image signals; 442R and 442G, switching circuits; 443, adelay circuit; 444R and 444G, switching circuits; 445, an input terminalfor a mode select signal; and 446R, 446G and 446B, output terminals forimage signals.

The operation of a liquid crystal display device according to thefifteenth embodiment of the present invention will now be describedwhile referring to FIGS. 24 and 17. The signal processing circuit 402performs a predetermined process on an image signal that is input at theinput terminal 401. The processed signal is transmitted to thesynchronizing separation circuit 403, which separates a synchronizationsignal from the received signal. The separated synchronization signal istransmitted to the controller 404. In response to the signal, thecontroller 404 supplies, to the X-driver 405 and the Y-driver 406, apredetermined drive pulse, for driving the LCD 407, that is synchronizedwith an image signal. The image signal output by the signal processingcircuit 402 is supplied across the delay circuit 411 to the X-driver405. The LCD 407 is driven by an image signal and a drive pulse, whichare supplied by the X-driver 405, and a drive pulse that is supplied bythe Y-driver 406, and character information is displayed on the LCD 407with an image at the same time.

In addition, the character region discrimination circuit 412 identifiesa region in which characters are included and a region in whichcharacters are not included, and supplies to the input terminal of theX-driver 405 a mode select signal. More specifically, the characterregion discrimination circuit 412 connects the switching circuits 442R,442G, 444R and 444G across side a for a region in which characters aredisplayed on a screen, and connects the switching circuits 442R, 442G,444R and 444G across side b for a region in which characters are notdisplayed. The delay circuit 443 provides a delay that is equivalent toone pixel of the LCD 407. Thus, when the switching circuits 442R, 442G,444R and 444G are connected across side a, image signal G, which isoutput at the output terminal 446G, is delayed by one pixel relative toimage signal B, which is output at the output terminal 446B, and signalR, which is output at the output terminal 446R, is delayed by two pixelsrelative to signal B. When the switching circuits 442R, 442G, 444R and444G are connected across side b, signals that are input at the inputterminals 441R, 441G and 441B are sent unchanged to the output terminals446R, 446G and 446B.

In this embodiment, since the X-driver 405 shown in FIG. 33A isemployed, in the LCD 407 sampling is performed for R, G and B pixels atthe same phase. However, when an image signal passes through the delaycircuit 411, a delay process is performed for the image signal in aregion in which characters are not displayed, so that the same effect asis obtained by sampling R, G and B pixels at different phases isacquired. Further, since an image signal for a region in whichcharacters are not displayed does not pass through the delay circuit 411and thus a delay process is not performed for that signal, sampling isperformed for R, G and B pixels at the same phase. The operationhereinafter is the same as that in the thirteenth embodiment, and nofurther explanation will be given.

As is described above, in a liquid crystal display device which addscharacter information to an input image for a display, a conventionalX-driver is applied, and as in the thirteenth and fourteenthembodiments, for a region in which characters are not displayed,sampling is performed at different phases for image signals relative toR, G and B pixels. For a region in which characters are displayed,sampling is performed at the same phase for R, G and B pixels. As aresult, the resolution in a region in which an image is displayed isincreased, and an occurrence of folded distortion can be prevented whencharacters are to be displayed.

As a modification of this embodiment, the delay circuit 411 in FIG. 24may have the arrangement shown in FIG. 18. Reference numbers 451R, 451Gand 451B denote input terminals for image signals; 452, a sample-holdcircuit; and 453R, 453G and 453B, output terminals for image signals.For a region in which characters are not displayed, the controller 404transmits to the delay circuit 411 sample-hold pulses shown in FIG. 19A.The phase of each pulse is shifted by one pixel of the LCD. Thus, in thedelay circuit shown in FIG. 17, image signal G, which is output at theoutput terminal 453G, is delayed by one pixel relative to signal B,which is output at the output terminal 453B, and signal R, which isoutput at the output terminal 453R, is delayed by two pixels. For aregion in which characters are displayed, pulses shown in FIG. 19B aresupplied. By making the sample-hold circuits 452 pass signals through,image signals that are input at the input terminals 451R, 451G and 451Bare output unchanged to the output terminals 453R, 453G and 453B.

Since the delay circuit is designed with sample-hold circuits, thisarrangement can easily cope with a change in the number of pixels in theLCD.

Sixteenth Embodiment!

The arrangement for a liquid crystal display device according to asixteenth embodiment of the present invention is the same as that shownin FIG. 16 for the fifteenth embodiment, except that the X-driver 405 inFIG. 34 and the delay circuit 411 in FIG. 20 are employed. The operationfor the ninth embodiment is also the same as that for the eighthembodiment, except for the control of these components, and noexplanation for it will be given. The same reference numbers as are usedin FIG. 17 are also used in FIG. 20 to denote corresponding or identicalcomponents. For a region in which characters are displayed, switchingcircuits 442B, 442G, 444B and 444G are connected across side a inconsonance with a control signal from a character region discriminationcircuit 412. For a region in which characters are not displayed, theseswitching circuits are connected across side b. Since the X-driver 405is designed as is shown in FIG. 34, an LCD 407 performs sampling for R,G and B pixels at different timings. Since a delay process is notperformed for an image signal for a region in which characters are notdisplayed, sampling is performed for R, G and B pixels at differentphases. Since an image signal for a region in which characters aredisplayed passes through the delay circuit 411 and thus a delay processis performed for that signal, the same effect as is obtained by samplingthe three pixels at the same phase can be acquired.

In this manner, the effect obtained in the fifteenth embodiment can alsobe acquired in this embodiment.

As well as in the fifteenth embodiment, the delay circuit 411 shown inFIG. 21 may be employed, and sample-hold pulses shown in FIGS. 22A and22B may be supplied. In addition, sample-hold pulses in FIG. 22A can besupplied for a region in which characters are not displayed, and pulsesin FIG. 22B can be supplied for a region in which characters aredisplayed.

As is described above, according to the present invention, in a liquidcrystal display device which adds character information to an inputimage for a display, for a region in which characters are not displayed,sampling is performed at different phases for image signals relative toR, G and B pixels. For a region in which characters are displayed,sampling is performed at the same phase for R, G and B pixels. As aresult, the resolution in a region in which an image is displayed isincreased, and an occurrence of folded distortion can be prevented whencharacters are to be displayed.

Further, in a liquid crystal display device which adds characterinformation to an input image for a display, a conventional X-driver canbe applied without any modification.

What is claimed is:
 1. A display device, which displays red, green andblue pixels in consonance with signal values that are acquired bysampling red, green and blue signals that are included in an input imagesignal during a predetermined cycle, comprising:detection means fordetecting a change value |A-B| between continuous signal values A and Bthat are acquired by sampling; first comparison means for comparing saidsignal value A with predetermined value L0; second comparison means forcomparing said change value |A-B | with predetermined value D0; andreplacement means for, in consonance with results of comparisons by saidfirst and second comparison means, replacing a signal value, which is tobe provided for a pixel for a specific color, with a signal value foranother color.
 2. A display device according to claim 1, wherein, when aresult of a comparison by said first comparison means is A<L0, and aresult of a comparison by said second comparison means is |A-B|>D0, saidreplacement means performs replacement of a signal value.
 3. A displaydevice which displays red, green and blue pixels in consonance withsignal values that are acquired by sampling red, green and blue signalsthat are included in an input image signal during a predetermined cycle,comprising:detection means for detecting a change value |A-B | betweentwo signal values A and B that are acquired by sampling; means forcomparing a predetermined comparison value in consonance with saidsignal value A; comparison means for comparing said change value |A-B |with said comparison value; and means for, in consonance with results ofcomparisons by said comparison means, replacing a signal value, which isto be provided for a pixel for a specific color, with a signal value foranother color.
 4. A display device which acquires red, green and bluesignal values by sampling, during a predetermined cycle, for red, greenand blue signals that are included in an input image signal, and whichsequentially allocates said signal values for pixels of correspondingcolors at each timing that is consonance with said cycle,comprising:detection means for, in consonance with sequential signalvalues and a change value for at least one color that are acquired bysampling, determining that color moire is noticeable; and means, when itis determined that said color moire is noticeable, for allocating asignal value for a specific color to a pixel for a different color,instead of a signal value for said pixel for said different color.
 5. Adisplay device which performs sampling of an input image signal during apredetermined cycle and supplies the sampled signals to pixels for threecolors, red, green and blue that are arranged in a matrix form,comprising:sampling means for sequentially performing sampling ofsignals for red, green and blue display pixels in said input imagesignal as time elapses, and for respectively acquiring first throughthird red signal values rn1, rn2 and rn3, first through third greenvalues gn1, gn2 and gn3 and first through third blue values bn1, bn2 andbn3; and selection means for selecting three signal values from amongsaid thus acquired signal values and for comparing a difference betweentwo signal values, which are selected from among said signal valuesobtained by sampling, with a predetermined value, and selecting andoutputting three signal values in consonance with a result of saidcomparison.
 6. A display device according to claim 5, wherein, when saidselection means compares a difference |rn1-rn2| between said first andsecond red signal values rn1 and rn2 with threshold value Th, and as aresult |rn1-rn2|>Th is established, or when said selection meanscompares a difference |rn2-rn3| between said second and third red signalvalues rn2 and rn3 with said threshold value Th, and as a result|rn2-rn3|>Th is established, said selection means selectively switches asignal value.
 7. A display device according to claim 6, wherein, inconsonance with the result of a comparison, said selection means changessaid first red signal rn1 and said third-blue signal value bn3 to saidsignal value gn1, gn2 or gn3.
 8. A display device according to claim 5,wherein, when said selection means compares a difference |gn1-gn2|between said first and second green signal values gn1 and gn2 with saidthreshold value Th, and as a result |gn1-gn2|>Th is established, or whensaid selection means compares a difference |gn2-gn3| between said secondand third green signal values gn2 and gn3 with said threshold value Th,and as a result |gn2-gn3|>Th is established, said selection meansselectively switches a signal value.
 9. A display device according toclaim 5, wherein, when said selection means compares a difference|bn1-bn2| between said first and second blue signal values bn1 and bn2with said threshold value Th, and as a result |bn1-bn2|>Th isestablished, or when said selection means compares a difference|bn2-bn3| between said second and third blue signal values bn2 and bn3with said threshold value Th, and as a result |bn2-bn3|>Th isestablished, said selection means selectively switches a signal value.10. A display device according to claim 5, wherein, when said selectionmeans compares a difference |rn1-gn2 | between said first red signalvalue rn1 and said second green signal value gn2 with said thresholdvalue Th, and as a result |rn1-gn2|>Th is established, or when saidselection means compares a difference |gn2-bn3| between said secondgreen signal value gn2 and said third blue signal value bn3 with saidthreshold value Th, and as a result |gn2-bn3|>Th is established, saidselection means selectively switches a signal value.
 11. A displaydevice according to any one of claims 5 to 7, wherein said samplingmeans performs sampling for red, green and blue control signals at saidtimes t1, t2 and t3 in order for the individual colors, and as a result,acquires further signal values Frn1, Frn2 and Frn3, Fgn1, Fgn2 and Fgn3,and Fbn1, Fbn2 and Fbn3, in consonance with the result of comparison,said selection means selects Frn1, Fgn2 and Fbn3 from among said signalvalues.
 12. A display device which performs sampling of image signalsfor colors different from each other and which applies the sampledsignals to pixels of colors different from each other arranged in anadjacent relation, comprising:a first circuit for supplying a modeswitching signal for switching a sampling mode; and a second circuit forchanging a sampling timing according to the mode switching signal,wherein when a character is to be displayed, the image signals forcolors different from each other inputted in time series are sampledsimultaneously and supplied to the pixels for colors different from eachother arranged in the adjacent relation, and when non-character contentsare to be displayed, the image signals for colors different from eachother inputted in time series are sampled in sequence and supplied tothe pixels for colors different from each other arranged in adjacentrelation.
 13. A display device according to claim 12, wherein said inputimage signals are a luminance signal and red, green and blue signals.14. A display device according to claim 12, wherein said input imagesignals are red, green and blue signals.
 15. A display device accordingto claim 12, further comprising a display element is a liquid crystalelement.
 16. A display device according to claim 15, wherein saiddisplay element has a diagonal measurement of 10 cm or smaller in screensize.
 17. A display device according to claim 12, further comprising adetection circuit for determining that said input image signals includecharacter information.
 18. A display device according to claim 12,further comprising means for synthesizing character information andnon-character information.
 19. A display device according to claim 12,further comprising a detection circuit that detects a change of aluminance signal or of at least one color signal.
 20. A display deviceaccording to claim 12, further comprising signal level detection meansfor detecting signal levels of a luminance signal and a color signal.21. A display device according to claim 12, further comprising signallevel change detection means for detecting a degree of a change ofsignal levels of a luminance signal and a color signal.
 22. A displaydevice according to claim 12, further comprising frequency detectionmeans for detecting frequency elements of a luminance signal and a colorsignal.
 23. A display device according to claim 12, further comprising:acharacter generation circuit for generating character information to bedisplayed; and a synthesizing circuit for synthesizing the characterinformation and the image signal.
 24. A display device according toclaim 12, wherein said second circuit is a switch provided m-stage flipflop and an output terminal.
 25. A display device according to claim 12,wherein said first circuit for supplying the mode switching signal is adiscrimination circuit for discriminating the character information andthe non-character information from the image signal inputted.
 26. Adisplay device which performs sampling of image signals for colorsdifferent from each other, and which supplies the sampling signal topixels for colors different from each other arranged in an adjacentrelation comprising:a first circuit for supplying a mode switchingsignal for switching a sampling mode; a second circuit for changing asampling timing according to the mode switching signal; and a delaycircuit, wherein when non-character contents are to be displayed, one ofthe image signals for colors different from each other inputted in timeseries is relatively delayed, and the image signals are sampledsimultaneously and supplied to the pixels for colors different from eachother arranged in the adjacent relation, and when a character is to bedisplayed, the image signals for colors different from each otherinputted in the time series are sampled simultaneously without relativedelaying and are supplied to the pixels for colors different from eachother arranged in the adjacent relation.
 27. A display device accordingto claim 26, wherein said circuit for delaying the image signal is asample hold circuit.
 28. A display device according to claim 26, whereinsaid first circuit for supplying the mode switching signal is adiscrimination circuit for discriminating the character information andthe non-character information from the image signal inputted.
 29. Adisplay device according to claim 26, wherein said input image signalsare a luminance signal and red, green and blue signals.
 30. A displaydevice according to claim 26, wherein said input image signals are red,green and blue signals.
 31. A display device according to claim 26,further comprising a display element having a liquid crystal element.32. A display device according to claim 31, wherein said display elementhas a diagonal measurement of 10 cm or smaller in screen size.
 33. Adisplay device according to claim 26, further comprising a detectioncircuit for determining that said input image signals include characterinformation.
 34. A display device according to claim 26, furthercomprising means for synthesizing character information andnon-character information.
 35. A display device according to claim 26,further comprising a detection circuit that detects a change of aluminance signal or of at least one color signal.
 36. A display deviceaccording to claim 26, further comprising signal level detection meansfor detecting signal levels of said luminance signal and said colorsignal.
 37. A display device according to claim 26, further comprisingsignal level change detection means for detecting a degree of a changeof signal levels of said luminance signal and said color signal.
 38. Adisplay device according to claim 26, further comprising frequencydetection means for detecting frequency elements of said luminancesignal and said color signal.
 39. A display device which performssampling of image signals for colors different from each other and whichsupplies the sampling signal to pixels for colors different from eachother arranged in an adjacent relation comprising:a first circuit forsupplying a mode switching signal for switching a sampling mode; asecond circuit for changing a sampling timing according to the modeswitching signal; and a delay circuit, wherein when a character is to bedisplayed, one of the image signals for colors different from each otherinputted in time series is relatively delayed, and the image signals aresampled in sequence and supplied to the pixels for colors different fromeach other arranged in the adjacent relation, and when non-charactercontents are to be displayed, the image signals for colors differentfrom each other inputted in the time series are sampled in sequencewithout relative delaying and are supplied to the pixels for colorsdifferent from each other arranged in the adjacent relation.
 40. Adisplay device according to claim 39, wherein said circuit for delayingthe image signal is a sample hold circuit.
 41. A display deviceaccording to claim 39, wherein said first circuit for supplying the modeswitching signal is a discrimination circuit for discriminating thecharacter information and the non-character information from the imagesignal inputted.
 42. A display device according to claim 39, whereinsaid input image signals are a luminance signal and red, green and bluesignals.
 43. A display device according to claim 39, wherein said inputimage signals are red, green and blue signals.
 44. A display deviceaccording to claim 39, further comprising a display element having aliquid crystal element.
 45. A display device according to claim 44,wherein said display element has a diagonal measurement of 10 cm orsmaller in screen size.
 46. A display device according to claim 39,further comprising a detection circuit for determining that said inputimage signals include character information.
 47. A display deviceaccording to claim 39, further comprising means for synthesizingcharacter information and non-character information.
 48. A displaydevice according to claim 39, further comprising a detection circuitthat detects a change of a luminance signal or of at least one colorsignal.
 49. A display device according to claim 39, further comprisingsignal level detection means for detecting signal levels of saidluminance signal and said color signal.
 50. A display device accordingto any one of claims 20, 36 or 49, further comprising character regiondiscrimination means for determining that a display image is a region inwhich character information is included when said signal level of saidluminance signal that is detected by said signal level detection meansis higher than a predetermined value, and when said signal level of saidcolor signal is lower than a predetermined value.
 51. A display deviceaccording to claim 39, further comprising signal level change detectionmeans for detecting a degree of a change of signal levels of saidluminance signal and said color signal.
 52. A display device accordingto any one of claims 21, 37 or 51 further comprising character regiondiscrimination means for determining that a display image is a region inwhich character information is included when said degree of a change ofsaid signal level of said luminance signal that is detected by saidsignal level change detection means is higher than a predetermined valueand when said degree of a change of said signal level of said colorsignal is lower than a predetermined value.
 53. A display deviceaccording to claim 39, further comprising frequency detection means fordetecting frequency elements of said luminance signal and said colorsignal.
 54. A display device according to any one of claims 22, 38 or53, further comprising character region discrimination means fordetermining that a display image is a region in which characterinformation is included when said frequency of said luminance signalthat is detected by said frequency detection means is higher than apredetermined value and when said frequency of said color signal islower than a predetermined value.
 55. A display device for samplingimage signals for red, green and blue, and supplying the image signalsto pixels for red, green and blue arranged in an adjacent relation,comprising:first means for sampling simultaneously the image signals forred, green and blue; second means for sampling a luminance signal; meansfor selecting one from among the image signal for red sampled in a firsttiming and the image signal for green sampled in a second timing, andfor selecting one from among the image signal for green sampled in thesecond timing and the image signal for blue sampled in a third timing;and comparing means for calculating a difference between the luminancesignals sampled in the first, second and third timings, and comparingthe difference with a predetermined threshold value, whereina) when thedifference of the luminance signals sampled in the first and secondtimings is smaller than a predetermined value, the image signal for redsampled in the first timing is supplied to the red pixel while, when thedifference is larger than the predetermined value, the image signal forgreen sampled in the second timing is supplied to the red pixel, b) theimage signal for green sampled in the second timing is supplied to thegreen pixel, and c) the difference between the luminance signals sampledin the second and third timings is smaller than the predetermined value,the image signal for blue sampled in the third timing is supplied to theblue pixel while, when the difference is larger than the predeterminedvalue, the image signal for green sampled in the second timing issupplied to the blue pixel.
 56. A display device for sampling imagesignals for red, green and blue, and supplying the image signals topixels for red, green and blue arranged in an adjacent relation,comprising:means for sampling simultaneously the image signals for red,green and blue; means for selecting one from among the image signal forred sampled in a first timing and the image signal for green sampled ina second timing, and for selecting one from among the image signal forgreen sampled in the second timing and the image signal for blue sampledin a third timing; and comparing means for calculating a differencebetween the image signals for green sampled in the first, second andthird timings, and comparing the difference with a predeterminedthreshold value, whereina) when the difference of the image signals forgreen sampled in the first and second timings is smaller than apredetermined value, the image signal for red sampled in the firsttiming is supplied to the red pixel while, when the difference is largerthan the predetermined value, the image signal for green sampled in thesecond timing is supplied to the red pixel, b) the image signal forgreen sampled in the second timing is supplied to the green pixel, andc) the difference between the image signals for green sampled in thesecond and third timings is smaller than the predetermined value, theimage signal for blue sampled in the third timing is supplied to theblue pixel while, when the difference is larger than the predeterminedvalue, the image signal for green sampled in the second timing issupplied to the blue pixel.